Patents by Inventor En Wang

En Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9122292
    Abstract: An LDO/HDO circuit adds a supplementary current source to supply the output node. The current boosting section includes a digital comparator with a first input connected to the LDO's feedback loop and a second input connected to a reference level. The comparator then generates a digital output used to control the supplementary current source. This approach also can be used in a far-side implementation, where the local supply level for the load is boosted by the current source based a comparison of this local level and the output of the LDO. Miller capacitive compensation is also considered. Current in shunted to ground from a node in the Miller loop, where the level is controlled by the output of a digital comparator base on a comparison of the circuit's output voltage and a reference level.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: September 1, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Feng Pan, Sung-En Wang, Jiang Yin
  • Publication number: 20150228351
    Abstract: To maintain stability of memory array operations, a supplemental current can supply a common source line of a memory array so that the combined current from the memory array and supplemental current is at least a minimum regulation current level. When enabled for sensing operations, a driver circuit maintains the common source line's voltage level. A current subtractor circuit determines the difference between a reference current and a current proportional to the current flowing from the array, where the reference current is proportional to the minimum regulation current. The difference current is then mirrored by a self-adjusting current loop and supplied to the common source line to maintain its current level.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 13, 2015
    Applicant: SanDisk Technologies Inc.
    Inventors: Sung-En Wang, Jonathan Huynh, Steve Choi, Jongmin Park
  • Publication number: 20150214964
    Abstract: A circuit for providing a plurality of clock signals of differing frequencies includes: a phase locked loop section including a first voltage controller oscillator, connected to receive a reference clock value and generate therefrom a first voltage level, wherein the first voltage controller oscillator receives the first voltage level and generates therefrom a first clock signal; and one or more second voltage controller oscillators, each connected to receive the first voltage level, a corresponding trim value and a corresponding control voltage and derive therefrom a corresponding second clock signal.
    Type: Application
    Filed: January 14, 2015
    Publication date: July 30, 2015
    Inventors: Jonathan Huynh, Sung-En Wang, Steve Choi, Jongmin Park
  • Patent number: 9083231
    Abstract: Techniques are presented for improving the efficiency of charge pumps. A charge pump, or a stage of a charge pump, provides its output through a pass gate. For example, this could be a charge pump of a voltage doubler type, where the output is supplied through pass gate transistors whose gates are connected to receive the output of an auxiliary section, also of a voltage doubler type of design. The waveforms provided to the gates of the pass gate transistors are modified so that their low values are offset to a higher value to take into account the threshold voltage of the pass gate transistors. In a voltage doubler based example, this can be implemented by way of introducing diodes into each leg of the auxiliary section.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: July 14, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Feng Pan, Jonathan Huynh, Sung-En Wang, Bo Lei
  • Publication number: 20150171664
    Abstract: A control method for implementation in a power supply system includes steps (A), (B), and (C). In step (A), while the power supply system is providing electricity to a load, a control circuit determines, an estimated capacitance value related to an output capacitor. In step (B), while the output capacitor is providing electricity to the load, the control circuit determines an average power value related to the electricity provided by the output capacitor to the load. In step (C), the control circuit determines an estimated hold-up time value related to the power supply system based on a predetermined target voltage value, a predetermined minimum voltage value, the average power value and the estimated capacitance value.
    Type: Application
    Filed: May 29, 2014
    Publication date: June 18, 2015
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORP.
    Inventors: YU-SHUN LIU, SHI-EN WANG
  • Publication number: 20150091637
    Abstract: Techniques are presented for improving the efficiency of charge pumps. A charge pump, or a stage of a charge pump, provides its output through a pass gate. For example, this could be a charge pump of a voltage doubler type, where the output is supplied through pass gate transistors whose gates are connected to receive the output of an auxiliary section, also of a voltage doubler type of design. The waveforms provided to the gates of the pass gate transistors are modified so that their low values are offset to a higher value to take into account the threshold voltage of the pass gate transistors. In a voltage doubler based example, this can be implemented by way of introducing diodes into each leg of the auxiliary section.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Applicant: SanDisk Technologies Inc.
    Inventors: Feng Pan, Jonathan Huynh, Sung-En Wang, Bo Lei
  • Publication number: 20150023100
    Abstract: To maintain stability of memory array operations, a current source supplies a common source line of a memory. The magnitude of the regulation current from the source is dynamically determined based on the amount of current from the array itself through use of a feedback control signal provided by a current comparator circuit. The current comparison circuit can use either a digital or an analog implementation.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 22, 2015
    Inventors: Jonathan H. Huynh, Sung-En Wang, Feng Pan
  • Patent number: 8928367
    Abstract: A pre-charging circuit, such as can be used to pre-charge a data bus, is largely process independent. A push-pull type of arrangement is used, where the output of the pre-charge circuit is initially connected to a supply level through one transistor, then connected to ground by another transistor. These transistors can be controlled by one or more comparators that have as inputs a reference level and feedback from the output. The reference level is generated by a circuit that tracks the threshold voltage of the other devices in the circuit in order to reduce process dependency of the output level. The circuit can also include a device to provide an extra VDD assist to the output.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: January 6, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Sung-En Wang, Feng Pan
  • Publication number: 20140375381
    Abstract: An amplifier system an amplified path and a bypass path for carrying an RF signal. A switch in the amplified system routes the RF signal through the amplified path in response to a normal condition in the amplifier system, and routes the RF signal through the bypass path in response to an abnormal condition in the amplifier system. The amplified path includes an amplified forward circuit and a return circuit. The amplified forward circuit has an amplifier, and the return circuit has a return amplifier and detection circuitry for providing power to the return amplifier. The detection circuity provides power to the return amplifier in response to a normal condition in the return circuit, and removes power from the return amplifier in response to an abnormal condition in the return circuit.
    Type: Application
    Filed: February 15, 2014
    Publication date: December 25, 2014
    Applicant: PCT International, Inc.
    Inventors: Kang Lin, Jon-En Wang
  • Patent number: 8842471
    Abstract: In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: September 23, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Hao Thai Nguyen, Juan Carlos Lee, Seungpil Lee, Masahide Matsumoto, Jongmin Park, Man Lung Mui, Sung-En Wang
  • Publication number: 20140254441
    Abstract: The present invention helps eliminate ingress noise addition (i.e., the “noise funneling effect” for an HFC coaxial plant). A system according to various aspects of the present invention comprises a switch that includes: (i) a first state for allowing passage of a signal therethrough; and (ii) a second state for preventing passage of the signal therethrough. The system further includes a detection circuit in communication with the switch. The detection circuit is configured to: (i) detect whether the signal includes an amplitude of at least a predetermined level; (ii) operate the switch to the first state if the amplitude of the signal is at least the predetermined level; and (iii) operate the switch to the second state if the amplitude of the signal is less than the predetermined level, wherein operation of the switch to the second state is delayed by a predetermined period of time.
    Type: Application
    Filed: May 20, 2014
    Publication date: September 11, 2014
    Applicant: PCT INTERNATIONAL, INC.
    Inventor: Jon-En Wang
  • Publication number: 20140240005
    Abstract: A pre-charging circuit, such as can be used to pre-charge a data bus, is presented that is largely process independent. A push-pull type of arrangement is used, where the output of the pre-charge circuit is initially connected to a supply level through one transistor, then connect to ground by another transistor. These transistors can be controlled by one or more comparators that have as inputs a reference level and feedback from the output. The reference level is generated by a circuit that tracks the threshold voltage of the other devices in the circuit in order to reduce process dependency of the output level. The circuit can also include a device to provide an extra VDD assist to the output.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Sung-En Wang, Feng Pan
  • Patent number: 8769597
    Abstract: The present invention helps eliminate ingress noise addition (i.e., the “noise funneling effect” for an HFC coaxial plant). A system according to various aspects of the present invention comprises a switch that includes: (i) a first state for allowing passage of a signal therethrough; and (ii) a second state for preventing passage of the signal therethrough. The system further includes a detection circuit in communication with the switch. The detection circuit is configured to: (i) detect whether the signal includes an amplitude of at least a predetermined level; (ii) operate the switch to the first state if the amplitude of the signal is at least the predetermined level; and (iii) operate the switch to the second state if the amplitude of the signal is less than the predetermined level, wherein operation of the switch to the second state is delayed by a predetermined period of time.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: July 1, 2014
    Assignee: PCT International, Inc.
    Inventor: Jon-En Wang
  • Publication number: 20140159682
    Abstract: An LDO/HDO circuit adds a supplementary current source to supply the output node. The current boosting section includes a digital comparator with a first input connected to the LDO's feedback loop and a second input connected to a reference level. The comparator then generates a digital output used to control the supplementary current source. This approach also can be used in a far-side implementation, where the local supply level for the load is boosted by the current source based a comparison of this local level and the output of the LDO. Miller capacitive compensation is also considered. Current in shunted to ground from a node in the Miller loop, where the level is controlled by the output of a digital comparator base on a comparison of the circuit's output voltage and a reference level.
    Type: Application
    Filed: January 25, 2013
    Publication date: June 12, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Feng Pan, Sung-En Wang, Jiang Yin
  • Publication number: 20140159683
    Abstract: An LDO/HDO circuit adds a supplementary current source to supply the output node. The current boosting section includes a digital comparator with a first input connected to the LDO's feedback loop and a second input connected to a reference level. The comparator then generates a digital output used to control the supplementary current source. This approach also can be used in a far-side implementation, where the local supply level for the load is boosted by the current source based a comparison of this local level and the output of the LDO. Miller capacitive compensation is also considered. Current in shunted to ground from a node in the Miller loop, where the level is controlled by the output of a digital comparator base on a comparison of the circuit's output voltage and a reference level.
    Type: Application
    Filed: January 25, 2013
    Publication date: June 12, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Feng Pan, Sung-En Wang, Jiang Yin
  • Patent number: 8730724
    Abstract: In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in NAND flash memory.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: May 20, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Tien-Chien Kuo, Jonathan H. Huynh, Sung-En Wang
  • Patent number: 8710914
    Abstract: Techniques are presented for improving the wake-up response of voltage regulation circuits. A first set of techniques relate to the inputs an op-amp in a regulation circuit. In regulated operation, one input receives feedback from the regulator's output. Instead, during reset, after resetting the op-amp's output node to the supply level, this input of op-amp is instead connected to ground in order to increase the amount of tail current through the op-amp in order to more quickly bring down the op-amp's output node. A detection circuit is introduced to determine when the op-amp's input is reconnected to receive feedback. In a complementary sets of techniques, when the circuit on which the regulator is formed receives an enable signal and the output of the regulator will be needed for an operation, and when the regulator is not yet back at operating levels, its supply is temporarily shorted to the supply level.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: April 29, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Shankar Guhados, Sung-En Wang, Feng Pan, Sagar Magia, Jonathan H. Huynh
  • Patent number: 8667550
    Abstract: A house amplifier provides automatic gating to selectively block the return path signal in a cable network. The house amplifier includes ports connected to the cable network and to at least one home coaxial outlet. A forward signal path is coupled to pass a forward signal from the cable network. A reverse signal path is coupled to selectively pass a reverse signal from the home to the cable network. The reverse signal path includes a gate configured to block the reverse signal in response to a control signal. A detector circuit detects when the reverse signal is received and activates or deactivates the gate based on the detection. The detector circuit may include a timing circuit configured to provide a delay before deactivating the gate when the reverse signal is no longer detected.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: March 4, 2014
    Assignee: PCT International, Inc.
    Inventor: Jon-En Wang
  • Publication number: 20140043898
    Abstract: In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in NAND flash memory.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 13, 2014
    Inventors: Tien-Chien Kuo, Jonathan H. Huynh, Sung-En Wang
  • Publication number: 20130176776
    Abstract: In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.
    Type: Application
    Filed: August 9, 2012
    Publication date: July 11, 2013
    Inventors: Hao Thai Nguyen, Juan Carlos Lee, Seungpil Lee, Masahide Matsumoto, Jongmin Park, Man Lung Mui, Sung-En Wang