Patents by Inventor Eng Huat Toh

Eng Huat Toh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10724983
    Abstract: A sensor device may include a substrate, first and second source regions, first and second drain regions, first and second channel regions, and first and second gate structures disposed over the first and second channel regions, respectively. The source regions and drain regions may be at least partially disposed within the substrate. The first and second source regions may have first and second source resistances, respectively, and the second source resistance may be higher than the first source resistance. The first gate structure may receive a solution, and a change in pH in the solution may cause a change in a first current flow through the first channel region. In turn, the second current flow through the second channel region may change to compensate for the change in the first current flow to maintain a constant current flow through the sensor device.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Bin Liu, Eng Huat Toh, Shyue Seng Tan, Ming Tsang Tsai, Khee Yong Lim, Kiok Boone Elgin Quek
  • Publication number: 20200235106
    Abstract: An anti-fuse memory cell may include a substrate including first and second conductivity regions and an isolation region at least partially within the substrate, a program gate over the substrate, a program gate oxide layer over the isolation region and between the program gate and the substrate, a first channel region arranged laterally between the first conductivity region and the isolation region, a second channel region arranged laterally between the second conductivity region and the isolation region, a first select gate arranged over the substrate and over the first channel region and a second select gate arranged over the substrate and over the second channel region. The program gate oxide layer may be configured to break down to allow conduction between the program gate and at least one of the channel regions upon providing a program voltage difference between the program gate and at least one of the channel regions.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 23, 2020
    Inventors: Xinshu CAI, Shyue Seng TAN, Eng Huat TOH
  • Patent number: 10720513
    Abstract: Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 21, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Kiok Boone Quek
  • Publication number: 20200220530
    Abstract: Provided are integrated circuits that include one or more magnetic tunnel junction ring oscillator(s) with tunable frequency and methods for operating the same. Accordingly, an integrated circuit is provided that includes a ring oscillator. The ring oscillator includes an input voltage terminal, an output voltage terminal, and an odd number of at least three inverters disposed electrically in series with one another between the input voltage terminal and the output voltage terminal. Each of the at least three inverters includes an NMOS transistor and one or more magnetic tunnel junctions (MTJs) disposed electrically in series with the NMOS transistor. The NMOS transistor of each of the at least three inverters is selectively tunable with regard to either or both of its threshold voltage and its effective channel width.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 9, 2020
    Inventors: Bin Liu, Eng Huat Toh
  • Patent number: 10707408
    Abstract: Methods of forming a high sensitivity Hall effect sensor having a thin Hall plate and the resulting devices are provided. Embodiments include providing a SOI substrate having a sequentially formed Si substrate and BOX and Si layers; forming a first STI structure in a first portion of the Si layer above the BOX layer, the first STI structure having a cross-shaped pattern; forming a second STI structure in a frame-shaped pattern in a second portion of the Si layer; the second STI structure formed outside and adjacent to the first STI structure; removing a portion of the Si layer between the first and second STI structures down to the BOX layer; removing the first STI structure, a cross-shaped Si layer remaining; and implanting N+ dopant ions into each end of the cross-shaped Si layer to form N+ implantation regions.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10700277
    Abstract: A memory device may include a bottom electrode, first and second switching elements over the bottom electrode, and first and second top electrodes over the first and second switching elements respectively. The first and second top electrodes may include first and second contact surfaces in contact with the first and second switching elements respectively. The first and second switching elements may each have a resistance configured to switch between resistance values in response to changes in voltages applied between the top electrodes and the bottom electrode. The bottom electrode may include at least one conductive layer having third and fourth contact surfaces in contact with the first and second switching elements respectively. An area of the first contact surface may be greater than an area of the third contact surface, and an area of the second contact surface may be greater than an area of the fourth contact surface.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Eng Huat Toh
  • Publication number: 20200203597
    Abstract: In a non-limiting embodiment, a magnetic memory device includes a memory component having a plurality of magnetic storage elements for storing memory data, and one or more sensor components configured to detect a magnetic field external to the memory component. The sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field. The memory component is configured to be terminated when the signal is above a predetermined threshold value. In some embodiments, a magnetic field is generated in a direction opposite to the direction of the detected external magnetic field when the signal is above the predetermined threshold value.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Bin Liu, Eng Huat Toh, Samarth Agarwal, Ruchil Kumar Jain, Kiok Boone Elgin Quek
  • Patent number: 10692920
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a photodetector, where the photodetector includes an impingement photodetector well and a base photodetector well. A transfer transistor overlies the photodetector, where the transfer transistor includes a transfer gate, a source, and a drain. A source contact is electrically connected to the source, and the source contact is also electrically connected to the photodetector.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ping Zheng, Eng Huat Toh
  • Patent number: 10693445
    Abstract: Provided are integrated circuits that include one or more magnetic tunnel junction ring oscillator(s) with tunable frequency and methods for operating the same. Accordingly, an integrated circuit is provided that includes a ring oscillator. The ring oscillator includes an input voltage terminal, an output voltage terminal, and an odd number of at least three inverters disposed electrically in series with one another between the input voltage terminal and the output voltage terminal. Each of the at least three inverters includes an NMOS transistor and one or more magnetic tunnel junctions (MTJs) disposed electrically in series with the NMOS transistor. The NMOS transistor of each of the at least three inverters is selectively tunable with regard to either or both of its threshold voltage and its effective channel width.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bin Liu, Eng Huat Toh
  • Patent number: 10685970
    Abstract: A method of forming a low-cost and compact hybrid SOI and bulk MTP cell and the resulting devices are provided. Embodiments include forming a bulk region in a SOI wafer; forming an NW in the bulk region and a PW in a remaining SOI region of the SOI wafer; forming first and second pairs of common FG stacks over both of the SOI and bulk regions; forming a first shared N+ RSD between each common FG stack of the first and second pairs in a top Si layer; forming a N+ RSD in the top Si layer of the SOI region on an opposite side of each common FG stack from the first shared N+ RSD; forming a second shared N+ RSD between each common FG stack in the bulk region; and forming a P+ RSD between the first and second pairs in the bulk region.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Danny Pak-Chum Shum
  • Publication number: 20200182826
    Abstract: A sensor device may include a substrate, first and second source regions, first and second drain regions, first and second channel regions, and first and second gate structures disposed over the first and second channel regions, respectively. The source regions and drain regions may be at least partially disposed within the substrate. The first and second source regions may have first and second source resistances, respectively, and the second source resistance may be higher than the first source resistance. The first gate structure may receive a solution, and a change in pH in the solution may cause a change in a first current flow through the first channel region. In turn, the second current flow through the second channel region may change to compensate for the change in the first current flow to maintain a constant current flow through the sensor device.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Bin LIU, Eng Huat TOH, Shyue Seng TAN, Ming Tsang TSAI, Khee Yong LIM, Kiok Boone Elgin QUEK
  • Publication number: 20200176513
    Abstract: A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. A second voltage line, and third and fourth voltage lines may be electrically coupled to a first conductivity region and a second conductivity region respectively. Resistive units may be arranged between the third and fourth voltage lines and the second conductivity region. In use, changes in voltages applied between the second and third voltage lines, and between the second and fourth voltage lines may cause resistances of first and second resistive units to switch between lower and higher resistance values. The lower resistance value of the first resistive unit may be different from the lower resistance value of the second resistive unit and/or the higher resistance value of the first resistive unit may be different from the higher resistance value of the second resistive unit.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Inventors: Lanxiang WANG, Shyue Seng TAN, Eng Huat TOH
  • Publication number: 20200173959
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a detection layer, a substrate, and a transistor having a transistor gate electrode, a transistor source, and a transistor drain. A capacitor gate electrode overlies the substrate, where the capacitor gate electrode and the transistor gate electrode are electrically connected with each other and with the detection layer. A capacitor well is defined within the substrate, and a gate insulator is positioned between the capacitor well and the capacitor gate electrode. A capacitor includes the capacitor gate electrode, the gate insulator, and the capacitor well.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 4, 2020
    Inventors: Eng Huat Toh, Bin Liu, Shyue Seng Tan, Kiok Boone Elgin Quek
  • Publication number: 20200161365
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a photodetector, where the photodetector includes an impingement photodetector well and a base photodetector well. A transfer transistor overlies the photodetector, where the transfer transistor includes a transfer gate, a source, and a drain. A source contact is electrically connected to the source, and the source contact is also electrically connected to the photodetector.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Ping Zheng, Eng Huat Toh
  • Patent number: 10651238
    Abstract: Multi-time programmable (MTP) random access memory (RRAM) devices and methods for forming a MTP RRAM device are disclosed. The method includes providing a substrate. The substrate is prepared with at least a first region for accommodating one or more multi-programmable based resistive random access memory (RRAM) cell. A fin-type based selector is provided over the substrate in the first region. A storage element of the RRAM cell is formed over the fin-type based selector. The fin-type based selector is coupled in series with the storage element of the RRAM cell.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xuan Anh Tran, Eng Huat Toh
  • Patent number: 10643725
    Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ping Zheng, Eng Huat Toh, Elgin Kiok Boone Quek
  • Publication number: 20200124565
    Abstract: A sensor device includes a substrate, first and second source regions, first and second drain regions, first and second channel regions, and first and second gate structures disposed over the first and second channel regions respectively. The source regions and drain regions are at least partially disposed within the substrate. The second gate structure includes first and second gate elements, and a resistance region configured to provide a resistance to a second current flow through the second channel region. In use, the first gate structure may receive a solution, and a change in pH in the solution changes a first current flow through the first channel region. In turn, the second current flow through the second channel region changes to compensate for the change in the first current flow to maintain a constant current flow through the sensor device.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 23, 2020
    Inventors: Lanxiang WANG, Ping ZHENG, Shyue Seng TAN, Eng Huat TOH
  • Patent number: 10629803
    Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; providing n-type dopant in the first and second n-type wells; and providing p-type dopant in the p-type well and the first n-type well.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bin Liu, Eng Huat Toh, Ruchil Kumar Jain
  • Publication number: 20200098769
    Abstract: Devices and methods of forming a device are disclosed. The device includes a substrate defined with at least a device region. A multi-gate transistor disposed in the device region which includes first and second gates both having first and second gate sidewalls. The multi-gate transistor also includes first source/drain (S/D) regions disposed adjacent to the first gate sidewall of the first and second gate, a common second S/D region disposed adjacent to the second gate sidewall of the first and second gate. A negative capacitance element is disposed within the second gate to reduce total overlap capacitance of the transistor. An interlevel dielectric (ILD) layer is disposed over the substrate and covering the transistor. First and second contacts are disposed in the ILD layer which are coupled to the first and second S/D regions respectively.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Shyue Seng TAN, Kiok Boone Elgin QUEK, Eng Huat TOH
  • Publication number: 20200098822
    Abstract: Magnetoresistive random access memory (MRAM) structures and arrays, methods for fabricating MRAM structures and arrays, and methods for operating MRAM structures and arrays are provided. An exemplary MRAM structure includes an access transistor having a source and a drain, a first magnetic tunnel junction (MTJ) element coupled to the source of the access transistor, and a second magnetic tunnel junction (MTJ) element coupled to the drain of the access transistor.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Inventors: Eng Huat Toh, Bin Liu, Kiok Boone Elgin Quek