Abstract: The present disclosure relates to sensors and, more particularly, to magnetic field sensors. More specifically, a structure includes a package with a wraparound geometry and discontinuous ends, and includes a low permeability magnetic material.

Abstract: The present disclosure provides a wafer probe card including: a non-magnetic printed circuit board (PCB) having a first side and a second side opposite the first side, the first side configured to face a magnet; a plurality of connection structures provided on the first side of the non-magnetic PCB; and a Hall sensor unit fixedly provided on the first side of the non-magnetic PCB, the Hall sensor electrically connected to at least one of the plurality of connection structures.

Abstract: A magnetic field sensor may include a semiconductor structure having a planar surface, and first, second, and third sensing devices. The semiconductor structure may include a semiconductor member having a two-dimensional electron gas therein, and an insulator member disposed on the semiconductor member. The first sensing device may be configured to sense magnetic field along a first axis parallel to the planar surface. The second sensing device may be configured to sense magnetic field along a second axis parallel to the planar surface, and orthogonal to the first axis. The third sensing device may be configured to sense a magnetic field along a third axis normal to the planar surface. Each of the first, second, and third sensing devices may be formed in the semiconductor structure and may include electrodes that extend from the insulator member to the two-dimensional electron gas.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an on-chip current sensor. The on-chip current sensor includes: a vertical Hall sensor; and a current carrying conductor in a first wiring layer above the vertical Hall sensor.

Abstract: The present disclosure relates to integrated circuits, and, more particularly, to a magnetic field sensor using magnetic tunneling junction (MTJ) structures and passive resistors, and methods of manufacture and operation. The structure includes: a first portion of a circuit including a first MTJ structure and a first resistor coupled in series between a first voltage source and a second voltage source; and a second portion of the circuit including a second MTJ structure and a second resistor coupled in series between the first voltage source and the second voltage source. The first portion and the second portion are coupled in parallel between the first voltage source and the second voltage source.

Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element has a first electrode, a second electrode, a third electrode, and a switching layer. The first electrode is coupled to the switching layer, the second electrode is coupled to a side surface of the switching layer, and the third electrode is coupled to the switching layer.

Abstract: The disclosed subject matter relates generally to structures, memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having two resistive layers and a conductive layer arranged between two electrodes. The present disclosure provides a memory device including a first electrode above an interlayer dielectric region, a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode, a conductive layer between the first electrode and the second electrode, in which the conductive layer is electrically isolated, a first resistive layer between the first electrode and the conductive layer, and a second resistive layer between the second electrode and the conductive layer.

Abstract: A magnetic field sensor may include a plurality of MTJ elements. Each MTJ element of has a state indicated by a magnetic moment direction of a sensing layer relative to a pinned, reference layer in an absence of an external magnetic field. The plurality of MTJ elements are arranged into two identical sets of at least two MTJ elements, where each MTJ element in each respective set has a different state. The states of the MTJ elements are arranged in a manner to measure the external magnetic field regardless of the direction of the external magnetic field. The MTJ elements include identical layers, and are electrically serially connected.

Abstract: A nonvolatile memory device is provided. The device comprises an active region, a floating gate over the active region and a wordline next to the floating gate. The floating gate has at least two narrow tips adjacent to the wordline and a portion of the floating gate between the narrow tips has a concave profile.

Abstract: Structures for an electronic fuse and methods of forming an electronic fuse. The structure includes a first terminal, a second terminal, and a fuse link extending from the first terminal to the second terminal. The structure further includes a silicide layer having a first portion included in the fuse link and a second portion included in the first terminal and the second terminal. The first portion of the silicide layer has a first thickness, the second portion of the silicide layer has a second thickness, and the first thickness is less than the second thickness.

Abstract: A non-volatile memory device and method of making the same is provided. The memory device includes a first electrode, a first hard mask on the first electrode, a second electrode on the first hard mask, a second hard mask on the second electrode, and a third electrode on the second hard mask. A switching layer is over the electrode stack and the switching layer has a first portion conformal to the side surfaces of the electrode stack.

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises an active region surrounded by an isolation structure. A floating gate may be arranged over the active region, the floating gate having a first end and a second end over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor may be provided, whereby a first electrode of the second capacitor is over the isolation structure and adjacent to the floating gate.

Abstract: Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.

Abstract: A memory device is provided. The memory device includes an active region in a substrate, an electrically-isolated electrode, and a dielectric layer. The electrically-isolated electrode is disposed over the active region. The dielectric layer is disposed between the electrically-isolated electrode and the active region and has a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.

Abstract: Structures for a photodetector and methods of forming a structure for a photodetector. The structure includes a semiconductor layer having a p-n junction and a deep trench isolation region extending through the semiconductor layer. The deep trench isolation region includes first layers and second layers that alternate with the first layers to define a Bragg mirror. The first layers contain a first material having a first refractive index, and the second layers contain a second material having a second refractive index that is greater than the first refractive index.

Abstract: The present disclosure provides a wafer probe card including: a non-magnetic printed circuit board (PCB) having a first side and a second side opposite the first side, the first side configured to face a magnet; a plurality of connection structures provided on the first side of the non-magnetic PCB; and a Hall sensor unit fixedly provided on the first side of the non-magnetic PCB, the Hall sensor electrically connected to at least one of the plurality of connection structures.

Abstract: The present disclosure relates to integrated circuits, and, more particularly, to a magnetic field sensor using magnetic tunneling junction (MTJ) structures and passive resistors, and methods of manufacture and operation. The structure includes: a first portion of a circuit including a first MTJ structure and a first resistor coupled in series between a first voltage source and a second voltage source; and a second portion of the circuit including a second MTJ structure and a second resistor coupled in series between the first voltage source and the second voltage source. The first portion and the second portion are coupled in parallel between the first voltage source and the second voltage source.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to temperature sensors with programmable magnetic tunnel junction structures and methods of manufacture. A structure includes a resistor material connected in series with a programmable magnetic tunnel junction structure in a Wheatstone bridge configuration.

Abstract: A memory device may be provided, including a substrate; one or more bottom electrodes arranged over the substrate; one or more switching layers arranged over the one or more bottom electrodes; and a plurality of top electrodes arranged over the one or more switching layers. Each of the one or more bottom electrodes may include at least one corner tip facing the switching layer, and an angle of each of the at least one corner tip may be less than ninety degrees.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate having an active region, a source region, a drain region, and a floating gate. The source region and the drain region may be arranged in the active region, the drain region may be arranged adjacent to the source region. The source region and the drain region may define a channel region therebetween.