Patents by Inventor Eng Huat Toh

Eng Huat Toh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor non-volatile memory devices
    Patent number: 11139311
    Abstract: A memory device is provided, which includes a substrate, a first memory cell, and a second memory cell. The first memory cell is arranged over the substrate and the second memory cell is arranged adjacent to the first memory cell. The first and second memory cells include a shared doped region arranged between the first and second memory cells.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: October 5, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yongshun Sun, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
  • HALL EFFECT SENSOR DEVICES AND METHODS OF FORMING HALL EFFECT SENSOR DEVICES
    Publication number: 20210286025
    Abstract: A Hall effect sensor device may be provided, including one or more sensor structures. Each sensor structure may include: a base layer having a first conductivity type; a Hall plate region having a second conductivity type opposite from the first conductivity type arranged above the base layer; a first isolating region arranged around and adjoining the Hall plate region, and contacting the base layer; a plurality of second isolating regions arranged within the Hall plate region; and a plurality of terminal regions arranged within the Hall plate region. The first and second isolating regions may include electrically insulating material, and each neighboring pair of terminal regions may be electrically isolated from each other by one of the second isolating regions.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Yongshun SUN, Eng Huat TOH, Ping ZHENG
  • MEMORY DEVICES AND METHODS OF FORMING MEMORY DEVICES
    Publication number: 20210273160
    Abstract: A memory device may be provided including one or more bottom electrodes, one or more mask elements, one or more top electrodes and a switching layer. The bottom electrode(s) may include a first bottom electrode, the mask element(s) may include a first mask element and the top electrode(s) may include a first top electrode. The first mask element may be arranged over a first part of the first bottom electrode. The first top electrode may be arranged over and in contact with the first mask element. The switching layer may be arranged to extend over a second part of the first bottom electrode, and along a first side surface of the first mask element and further along a first side surface of the first top electrode. The first side surfaces of the first mask element and the first top electrode may face a same direction.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: Desmond Jia Jun LOY, Eng Huat TOH, Shyue Seng TAN
  • SEMICONDUCTOR NON-VOLATILE MEMORY DEVICES
    Publication number: 20210257377
    Abstract: A memory device is provided, which includes a substrate, a first memory cell, and a second memory cell. The first memory cell is arranged over the substrate and the second memory cell is arranged adjacent to the first memory cell. The first and second memory cells include a shared doped region arranged between the first and second memory cells.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: YONGSHUN SUN, ENG HUAT TOH, SHYUE SENG TAN, KIOK BOONE ELGIN QUEK
  • Methods of forming a thyristor-based random access memory using fin structures and elevated layers
    Patent number: 11094696
    Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a well of a first polarity type and a thyristor-based memory cell. The thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate. At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: August 17, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Kiok Boone Quek, Danny Pak-Chum Shum
  • SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES
    Publication number: 20210247470
    Abstract: A semiconductor device may be provided including a first series portion and a second series portion electrically connected in parallel with the first series portion. The first series portion may include a first MTJ stack and a first resistive element electrically connected in series. The second series portion may include a second MTJ stack and a second resistive element electrically connected in series. The first resistive element may include a third MTJ stack and the second resistive element may include a fourth MTJ stack. The first, second, third, and fourth MTJ stacks may include a same number of layers, which may include a fixed layer, a free layer, and a tunnelling barrier layer between the fixed layer and the free layer. Alternatively, the first resistive element may include a first transistor and the second resistive element may include a second transistor.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Inventors: Ping ZHENG, Eng Huat TOH, Kazutaka YAMANE, Shyue Seng TAN, Kiok Boone Elgin QUEK
  • Memory cells with extended erase gate, and process of fabrication
    Patent number: 11088156
    Abstract: A flash memory device is provided. The device comprises a substrate and a source region in the substrate. A first gate stack is positioned above the substrate and adjacent to the source region. A dual function gate structure having an upper portion and a lower portion is positioned above the source region. The upper portion of the dual function gate structure overlaps the first gate stack and the lower portion is adjacent to the first gate stack. A second gate is positioned above the substrate on an opposite side of the first gate stack from the dual function gate. A drain region is in the substrate adjacent to the second gate.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 10, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Kiok Boone Elgin Quek, Eng Huat Toh
  • MEMORY DEVICES AND METHODS OF FORMING MEMORY DEVICES
    Publication number: 20210225936
    Abstract: A memory device may be provided, including a substrate; one or more bottom electrodes arranged over the substrate; one or more switching layers arranged over the one or more bottom electrodes; and a plurality of top electrodes arranged over the one or more switching layers. Each of the one or more bottom electrodes may include at least one corner tip facing the switching layer, and an angle of each of the at least one corner tip may be less than ninety degrees.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Inventors: Lanxiang WANG, Shyue Seng TAN, Eng Huat TOH, Benfu LIN
  • Non-volatile memory elements with a multi-level cell configuration
    Patent number: 11069743
    Abstract: Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. A first non-volatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A second non-volatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the second electrode of the first non-volatile memory element.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: July 20, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan
  • DUAL BIT MEMORY DEVICE WITH TRIPLE GATE STRUCTURE
    Publication number: 20210217865
    Abstract: A memory device is provided. The device comprises a semiconductor fin with a first gate and a second gate disposed over the semiconductor fin. A third gate is positioned over the semiconductor fin and a lower portion of the third gate is disposed between the first and second gates.
    Type: Application
    Filed: January 14, 2020
    Publication date: July 15, 2021
    Inventors: XINSHU CAI, SHYUE SENG TAN, ENG HUAT TOH
  • SEMICONDUCTOR DEVICES WITH MEMORY CELLS
    Publication number: 20210217859
    Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure provides a semiconductor device including an isolation region disposed on a substrate, a pair of diffusion structures disposed upon the isolation region, a dielectric layer that covers side surfaces of the diffusion structures, and a gate structure disposed on the dielectric layer and between the diffusion structures, where the gate structure is electrically coupled to the diffusion structures.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 15, 2021
    Inventors: WEI CHANG, ENG HUAT TOH, SHYUE SENG TAN
  • Sensors having resistive elements
    Patent number: 11063158
    Abstract: A sensor is provided, which includes a semiconductor substrate, a photodiode region, and a multi-layered resistive element. The photodiode region is arranged in the semiconductor substrate. The multi-layered resistive element is arranged over the semiconductor substrate and is coupled with the photodiode region.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 13, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
  • Semiconductor devices with ion-sensitive field effect transistor
    Patent number: 11054387
    Abstract: The present disclosure generally relates to semiconductor devices, and more particularly to semiconductor devices integrated with an ion-sensitive field-effect transistor (ISFET) and methods of forming the same. The semiconductor device may include a substrate, a reference gate structure disposed above the substrate, a floating gate structure disposed above the substrate and adjacent to the reference gate structure, where the reference gate structure is electrically coupled to the floating gate structure, and a dielectric layer disposed between the reference gate structure and the floating gate structure.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 6, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Eng Huat Toh
  • Hall effect sensors with tunable sensitivity and/or resistance
    Patent number: 11047930
    Abstract: A device having a Hall effect sensor is provided. The Hall effect sensor includes a sensor well and a Hall plate disposed within the sensor well. The Hall plate includes a first current terminal and a second current terminal configured to flow a current through the Hall plate, and the Hall plate further includes a first sensing terminal and a second sensing terminal configured to sense a Hall voltage. A separation layer and a separation well are disposed within the sensor well, as well as surround the Hall plate and isolate the Hall plate. At least one of a current sensitivity and a resistance of the Hall effect sensor is tunable based on an adjustable thickness of the Hall plate. The thickness of the Hall plate is adjustable based at least in part on implants in the separation layer and/or a bias voltage applied to the separation layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 29, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yongshun Sun, Eng Huat Toh, Kiok Boone Elgin Quek
  • Logic gate devices and methods of forming a logic gate device
    Patent number: 11050426
    Abstract: According to various embodiments, a logic gate device includes a transistor, a first resistor, a second resistor and a third resistor. The first resistor is connected between a first input terminal of the logic gate device and a gate terminal of the transistor. The second resistor is connected between a second input terminal of the logic gate device and the gate terminal. The third resistor is connected between a voltage supply terminal and a first terminal of the transistor. The logic gate device is configured to generate an output voltage at the first terminal based on input voltages received at the first input terminal and the second input terminal.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: June 29, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan
  • SENSORS HAVING RESISTIVE ELEMENTS
    Publication number: 20210184059
    Abstract: A sensor is provided, which includes a semiconductor substrate, a photodiode region, and a multi-layered resistive element. The photodiode region is arranged in the semiconductor substrate. The multi-layered resistive element is arranged over the semiconductor substrate and is coupled with the photodiode region.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: LANXIANG WANG, ENG HUAT TOH, SHYUE SENG TAN, KIOK BOONE ELGIN QUEK
  • ON-CHIP TEMPERATURE SENSING WITH NON-VOLATILE MEMORY ELEMENTS
    Publication number: 20210164845
    Abstract: Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Bin Liu, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
  • NON-VOLATILE MEMORY ELEMENTS WITH ONE-TIME OR MULTIPLE-TIME PROGRAMMABILITY
    Publication number: 20210167069
    Abstract: Structures for a non-volatile memory and methods of forming such structures. A gate electrode and a gate dielectric layer are formed over an active region with the gate dielectric layer between the gate electrode and the active region. A first doped region is formed in the active region, a second doped region is formed in the active region, and a source line is coupled to the second doped region. The first doped region is positioned in the active region at least in part beneath the gate dielectric layer, and the second doped region is positioned in the active region adjacent to the first doped region. The first doped region has a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Sriram Balasubramanian, Shyue Seng Tan
  • NON-VOLATILE MEMORY BIT CELLS WITH NON-RECTANGULAR FLOATING GATES
    Publication number: 20210159234
    Abstract: Structures for a non-volatile memory bit cell and methods of forming a structure for a non-volatile memory bit cell. A field-effect transistor has a channel region and a first gate electrode positioned over the channel region. A capacitor includes a second gate electrode that is coupled to the first gate electrode to define a floating gate. The first gate electrode has a non-rectangular shape.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Inventors: Lanxiang Wang, Shyue Seng Tan, Kiok Boone Elgin Quek, Xinshu Cai, Eng Huat Toh
  • MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE
    Publication number: 20210135101
    Abstract: A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Inventors: Desmond Jia Jun LOY, Eng Huat TOH, Shyue Seng TAN, Steven SOSS