Abstract: In a non-limiting embodiment, a magnetic memory device includes a memory component having a plurality of magnetic storage elements for storing memory data, and one or more sensor components configured to detect a magnetic field external to the memory component. The sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field. The memory component is configured to be terminated when the signal is above a predetermined threshold value. In some embodiments, a magnetic field is generated in a direction opposite to the direction of the detected external magnetic field when the signal is above the predetermined threshold value.

Abstract: A sensor device may include a substrate, and first and second semiconductor structures arranged over the substrate. The first semiconductor structure may be an ion-sensitive field effect transistor and may include a floating gate, and a sensing element electrically coupled to the floating gate. The second semiconductor structure may be capacitively coupled to the first semiconductor structure, and may include a first diffusion region and a second diffusion region having opposite polarity type dopants, and a channel region arranged therebetween. The second semiconductor structure may be configured to receive a bias voltage to tune an electrical characteristic of the first semiconductor structure through the first diffusion region and the second diffusion region and the channel region. In some embodiments, the substrate may be a crystalline-on-insulator substrate which may be coupled to a back gate bias to reduce an effective total capacitance of the ISFET and further improve the coupling ratio.

Abstract: Structures for a sensor and methods of forming such structures. A sensing element includes a free magnetic layer, a pinned magnetic layer, and a non-magnetic conductive spacer layer between the free magnetic layer and the pinned magnetic layer. A dummy element is positioned outside of an outer boundary of the sensing element. The dummy element is detached from the sensing element.

Abstract: According to various non-limiting embodiments a memory device may include a silicon-on-insulator layer having a conductivity of a first polarity, a first raised structure over the silicon-on-insulator layer, the second raised structure over the silicon-on-insulator layer, an dummy gate arranged between the first raised structure and the second raised structure, and a memory connected to the second raised structure. The first raised structure may have a conductivity of the first polarity, and the second raised structure may include a first diode layer having a conductivity of a second polarity opposite to the first polarity.

Abstract: Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a memory cell, wherein the memory cell includes a transistor having a source and a drain, a first resistive unit in electrical communication with the source, and a second resistive unit in electrical communication with the drain. The first resistive unit includes a first bottom electrode, a first top electrode, and a first resistive element positioned between the first bottom electrode and the first top electrode. The second resistive unit includes a second bottom electrode, a second top electrode, and a second resistive element positioned between the second bottom electrode and the second top electrode.

Abstract: Integrated circuits with magnetic random access memory (MRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a method for fabricating MRAM bitcells includes determining a desired inter-cell spacing between a first bitcell and a second bitcell and double patterning a semiconductor substrate to form semiconductor fin structures, wherein the semiconductor fin structures are formed in groups with an intra-group pitch between grouped semiconductor fin structures and with the inter-cell spacing between adjacent groups of semiconductor fin structures different from the intra-group pitch. The method further includes forming a first MRAM memory structure over the semiconductor fin structures in the first bitcell and forming a second MRAM memory structure over the semiconductor fin structures in the second bitcell. Also, the method includes forming a first source line for the first bitcell between the first MRAM memory structure and the second MRAM memory structure.

Abstract: Methods of forming a ferroelectric material layer below a field plate for achieving increased Vbr with reduced Rdson and resulting devices are provided. Embodiments include forming a N-Drift in a portion of the Si layer formed in a portion of a p-sub; forming an oxide layer over portions of the Si layer and the N-Drift; forming a gate over a portion of the oxide layer; forming a S/D extension region in the Si layer; forming first and second spacers on opposite sides of the gate and the oxide layer; forming a S/D region in the Si layer adjacent to the S/D extension region and a S/D region in the N-Drift remote from the Si layer; forming a U-shaped ferroelectric material layer over the oxide layer and the N-Drift, proximate or adjacent to the gate; and filling the U-shaped ferroelectric material layer with a metal, a field gate formed.

Abstract: Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.

Abstract: A device having a Hall effect sensor is provided. The Hall effect sensor includes a sensor well and a Hall plate disposed within the sensor well. The Hall plate includes a first current terminal and a second current terminal configured to flow a current through the Hall plate, and the Hall plate further includes a first sensing terminal and a second sensing terminal configured to sense a Hall voltage. A separation layer and a separation well are disposed within the sensor well, as well as surround the Hall plate and isolate the Hall plate. At least one of a current sensitivity and a resistance of the Hall effect sensor is tunable based on an adjustable thickness of the Hall plate. The thickness of the Hall plate is adjustable based at least in part on implants in the separation layer and/or a bias voltage applied to the separation layer.

Abstract: In a non-limiting embodiment, a magnetic memory device includes a memory component having a plurality of magnetic storage elements for storing memory data, and one or more sensor components configured to detect a magnetic field external to the memory component. The sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field. The memory component is configured to be terminated when the signal is above a predetermined threshold value. In some embodiments, a magnetic field is generated in a direction opposite to the direction of the detected external magnetic field when the signal is above the predetermined threshold value.

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a detection layer, a substrate, and a transistor having a transistor gate electrode, a transistor source, and a transistor drain. A capacitor gate electrode overlies the substrate, where the capacitor gate electrode and the transistor gate electrode are electrically connected with each other and with the detection layer. A capacitor well is defined within the substrate, and a gate insulator is positioned between the capacitor well and the capacitor gate electrode. A capacitor includes the capacitor gate electrode, the gate insulator, and the capacitor well.

Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.

Abstract: A sensor device may include a substrate, first and second source regions, first and second drain regions, first and second channel regions, and first and second gate structures disposed over the first and second channel regions, respectively. The source regions and drain regions may be at least partially disposed within the substrate. The first and second source regions may have first and second source resistances, respectively, and the second source resistance may be higher than the first source resistance. The first gate structure may receive a solution, and a change in pH in the solution may cause a change in a first current flow through the first channel region. In turn, the second current flow through the second channel region may change to compensate for the change in the first current flow to maintain a constant current flow through the sensor device.

Abstract: An anti-fuse memory cell may include a substrate including first and second conductivity regions and an isolation region at least partially within the substrate, a program gate over the substrate, a program gate oxide layer over the isolation region and between the program gate and the substrate, a first channel region arranged laterally between the first conductivity region and the isolation region, a second channel region arranged laterally between the second conductivity region and the isolation region, a first select gate arranged over the substrate and over the first channel region and a second select gate arranged over the substrate and over the second channel region. The program gate oxide layer may be configured to break down to allow conduction between the program gate and at least one of the channel regions upon providing a program voltage difference between the program gate and at least one of the channel regions.

Abstract: Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.

Abstract: Provided are integrated circuits that include one or more magnetic tunnel junction ring oscillator(s) with tunable frequency and methods for operating the same. Accordingly, an integrated circuit is provided that includes a ring oscillator. The ring oscillator includes an input voltage terminal, an output voltage terminal, and an odd number of at least three inverters disposed electrically in series with one another between the input voltage terminal and the output voltage terminal. Each of the at least three inverters includes an NMOS transistor and one or more magnetic tunnel junctions (MTJs) disposed electrically in series with the NMOS transistor. The NMOS transistor of each of the at least three inverters is selectively tunable with regard to either or both of its threshold voltage and its effective channel width.

Abstract: Methods of forming a high sensitivity Hall effect sensor having a thin Hall plate and the resulting devices are provided. Embodiments include providing a SOI substrate having a sequentially formed Si substrate and BOX and Si layers; forming a first STI structure in a first portion of the Si layer above the BOX layer, the first STI structure having a cross-shaped pattern; forming a second STI structure in a frame-shaped pattern in a second portion of the Si layer; the second STI structure formed outside and adjacent to the first STI structure; removing a portion of the Si layer between the first and second STI structures down to the BOX layer; removing the first STI structure, a cross-shaped Si layer remaining; and implanting N+ dopant ions into each end of the cross-shaped Si layer to form N+ implantation regions.

Abstract: A memory device may include a bottom electrode, first and second switching elements over the bottom electrode, and first and second top electrodes over the first and second switching elements respectively. The first and second top electrodes may include first and second contact surfaces in contact with the first and second switching elements respectively. The first and second switching elements may each have a resistance configured to switch between resistance values in response to changes in voltages applied between the top electrodes and the bottom electrode. The bottom electrode may include at least one conductive layer having third and fourth contact surfaces in contact with the first and second switching elements respectively. An area of the first contact surface may be greater than an area of the third contact surface, and an area of the second contact surface may be greater than an area of the fourth contact surface.