Patents by Inventor Eok Su Kim

Eok Su Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8395155
    Abstract: Thin film transistors (TFTs) and methods of manufacturing the same. A TFT may include a floating channel on a surface of a channel and spaced apart from a source and a drain, and an insulating layer formed on the floating channel and designed to determine a distance between the floating channel and the source or the drain.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: March 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eok-su Kim, Sang-yoon Lee, Myung-kwan Ryu, Kyung-bae Park
  • Publication number: 20130050802
    Abstract: In one embodiment, the electrowetting device includes a first medium; a second medium that is not mixed with the first medium and has a refractive index different from a refractive index of the first medium; an upper electrode that adjusts an angle of a boundary surface between the first medium and the second medium; and a barrier wall that has a side surface surrounding the first and second mediums, allows the upper electrode to be disposed on a portion of the side surface, and has irregular widths.
    Type: Application
    Filed: August 29, 2012
    Publication date: February 28, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-deok BAE, Jun-sik HWANG, Chang-youl MOON, Yoon-sun CHOI, Jung-mok BAE, Chang-seung LEE, Eok-su KIM
  • Publication number: 20130021388
    Abstract: A light refraction controlling panel, a 3D-display, and a method of operating a 3D-display are provided. The light refraction controlling panel includes a transparent substrate, a barrier wall on the transparent substrate, first to fourth electrodes on the barrier wall, the first to fourth electrodes being separated from each other, an electro-wetting prism within the barrier wall, the electro-wetting prism being configured to refract incident light to a desired direction, and an isolation layer between the barrier wall and the first to fourth electrodes, and the electro-wetting prism. One electrode of two adjacent electrodes of the first to fourth electrodes is inside an other electrode of the two adjacent electrodes.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 24, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-hwan Choi, Jung-mok Bae, Hoon Song, Sang-yoon Lee, Yoon-sun Choi, Eok-su Kim
  • Publication number: 20120307357
    Abstract: A three-dimensional (3D) image display apparatus and method are provided. The 3D image display apparatus includes an image generating unit configured to generate an image, an active optical device configured to change a propagation path of light containing the generated image, and provide the generated image to multiple viewpoints that are located along a first direction parallel to the image generating unit, and a varifocal lens configured to vary a focal position of the generated image along a second direction away from the image generating unit.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 6, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-hwan Choi, Hong-seok Lee, Hoon Song, Yoon-sun Choi, Jung-mok Bae, Eok-su Kim
  • Patent number: 8300027
    Abstract: A vibration touch sensor includes; a first substrate, a second substrate arranged to face the first substrate with a predetermined gap therebetween, a first electrode disposed on the first substrate, a second electrode disposed on the second substrate, a piezoelectric material layer disposed on one of the first electrode and the second electrode, wherein the piezoelectric material layer generates an electrical signal in response to an external touch applied to at least one of the first substrate and the second substrate, and a controller which receives the electrical signal generated from the piezoelectric material layer and generates a touch input signal, the controller controlling an alternating current voltage applied to at least one of the first electrode and the second electrode.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eok Su Kim, Jaeyoung Choi
  • Publication number: 20120256168
    Abstract: According to example embodiments, a semiconductor device includes a first electrode, a second electrode apart from the first electrode, and an active layer between the first and second electrodes. The active layer includes first and second layers, the first layer contacts the first and second electrodes, and the second layer is separated from at least one of the first and second electrodes.
    Type: Application
    Filed: September 23, 2011
    Publication date: October 11, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiyoul Lee, Eok-su Kim, Won-mook Choi, Sun-kook Kim
  • Publication number: 20120168757
    Abstract: A transistor includes a channel layer disposed above a gate and including an oxide semiconductor. A source electrode contacts a first end portion of the channel layer, and a drain electrode contacts a second end portion of the channel layer. The channel layer further includes a fluorine-containing region formed in an upper portion of the channel layer between the source electrode and the drain electrode.
    Type: Application
    Filed: June 21, 2011
    Publication date: July 5, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-bae Park, Myung-kwan Ryu, Kwang-hee Lee, Tae-sang Kim, Eok-su Kim, Kyoung-seok Son, Hyun-suk Kim, Wan-joo Maeng, Joon-seok Park
  • Publication number: 20120146713
    Abstract: A transistor includes a first active layer having a first channel region and a second active layer having a second channel region. A first gate of the transistor is configured to control electrical characteristics of at least the first active layer and a second gate is configured to control electrical characteristics of at least the second active layer. A source electrode contacts the first and second active layers. A drain electrode also contacts the first and second active layers.
    Type: Application
    Filed: June 23, 2011
    Publication date: June 14, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eok-su Kim, Sang-yoon Lee, Myung-kwan Ryu
  • Publication number: 20120025187
    Abstract: Transistors, methods of manufacturing the transistors, and electronic devices including the transistors. The transistor may include an oxide channel layer having a multi-layer structure. The channel layer may include a first layer and a second layer that are sequentially arranged from a gate insulation layer. The first layer may be a conductor, and the second layer may be a semiconductor having a lower electrical conductivity than that of the first layer. The first layer may become a depletion region according to a gate voltage condition.
    Type: Application
    Filed: March 24, 2011
    Publication date: February 2, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyung-bae Park, Hyun-suk Kim, Myung-kwan Ryu, Sang-yoon Lee, Kwang-hee Lee, Tae-sang Kim, Eok-su Kim, Kyoung-seok Son, Wan-joo Maeng, Joon-seok Park
  • Publication number: 20110180803
    Abstract: Thin film transistors (TFTs) and methods of manufacturing the same. A TFT may include a floating channel on a surface of a channel and spaced apart from a source and a drain, and an insulating layer formed on the floating channel and designed to determine a distance between the floating channel and the source or the drain.
    Type: Application
    Filed: January 26, 2011
    Publication date: July 28, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Eok-su Kim, Sang-yoon Lee, Myung-kwan Ryu, Kyung-bae Park
  • Publication number: 20110168999
    Abstract: A semiconductor wire grid may include a plurality of wires arranged separately on a substrate, formed of a semiconductor, and including a groove therebetween, wherein conductivity of the semiconductor wire grid varies according to an applied voltage such that a polarization rate of the semiconductor wire grid is controlled.
    Type: Application
    Filed: August 25, 2010
    Publication date: July 14, 2011
    Inventor: Eok-su Kim
  • Publication number: 20110155478
    Abstract: A thermoelectric touch sensor includes a first electrode, a thin film layer provided on the first electrode and including a thermoelectric material, a second electrode provided on the thin film layer, a sensing unit which senses at least one of a current flowing between the first electrode and the second electrode and a voltage applied between the first electrode and the second electrode.
    Type: Application
    Filed: June 30, 2010
    Publication date: June 30, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Duk-hyun CHOI, Jae-young CHOI, Eok-su KIM, Jong-soo RHYEE
  • Publication number: 20100156845
    Abstract: A vibration touch sensor includes; a first substrate, a second substrate arranged to face the first substrate with a predetermined gap therebetween, a first electrode disposed on the first substrate, a second electrode disposed on the second substrate, a piezoelectric material layer disposed on one of the first electrode and the second electrode, wherein the piezoelectric material layer generates an electrical signal in response to an external touch applied to at least one of the first substrate and the second substrate, and a controller which receives the electrical signal generated from the piezoelectric material layer and generates a touch input signal, the controller controlling an alternating current voltage applied to at least one of the first electrode and the second electrode.
    Type: Application
    Filed: December 1, 2009
    Publication date: June 24, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eok Su KIM, Jaeyoung CHOI
  • Publication number: 20100103121
    Abstract: A touch screen panel includes: a first substrate and a second substrate, which face each other with respect to a liquid crystal interposed therebetween; and a touch sensor interposed between the first substrate and the second substrate. The touch sensor includes: a plurality of first touch signal lines disposed on the first substrate and extending in a first direction; a protective layer disposed on the first substrate, the protective layer including a dielectric material and substantially the plurality of first touch signal lines; a plurality of contact pads disposed on the protective layer; a plurality of second touch signal lines disposed on the second substrate and extending in a second direction perpendicular to the first direction; and a plurality of touch sensor spacers electrically connected to the plurality of second touch signal lines. A gap between the touch sensor spacers and the plurality of contact pads is defined, and the spacers are disposed to face the plurality of contact pads.
    Type: Application
    Filed: April 29, 2009
    Publication date: April 29, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eok-su KIM, Jae-young CHOI, Won-mook CHOI, Duk-hyun CHOI
  • Patent number: 7678621
    Abstract: Disclosed are a crystallization pattern, and a method for crystallizing amorphous silicon. The method includes the steps of forming an amorphous silicon film on a glass substrate, forming a crystallization pattern by patterning the amorphous silicon film, and crystallizing the crystallization pattern into polycrystalline silicon by irradiating a laser onto the crystallization pattern. The crystallization pattern includes a peripheral region located within a first distance from an edge of the crystallization pattern, and an internal region located away from the edge of the crystallization pattern by more than the first distance. The internal region is divided into at least one sub-region, each sub-region includes one crystallization inducement pattern, and an edge of each sub-region is located within a second distance from the crystallization inducement pattern.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: March 16, 2010
    Assignee: Hydis Technologies, Co., Ltd
    Inventors: Myung Kwan Ryu, Eok Su Kim, Kyoung Seok Son, Jang Soon Im
  • Publication number: 20070238270
    Abstract: Disclosed is a method for forming a polycrystalline film. The method for forming a polycrystalline film from a film deposited on a glass substrate while a buffer layer is interposed between the deposited film and the glass substrate, which includes the steps of: preparing a mask including a transparent region having a larger size than that of resolution limitation of a laser beam equipment and an opaque region having a size which is smaller than that of the resolution limitation of the laser beam equipment; and irradiating laser beam of the maximum intensity to a film under the transparent region while irradiating the laser beam having a minimum intensity exceeding zero to the film under an opaque region by using the mask, thereby crystallizing the film by single irradiation of the laser beam.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 11, 2007
    Inventors: Eok Su Kim, Myung Kwan Ryu, Gon Son, Hyuk Soon Kwon, Jung Ho Park
  • Publication number: 20070218658
    Abstract: Disclosed are a crystallization pattern, and a method for crystallizing amorphous silicon. The method includes the steps of forming an amorphous silicon film on a glass substrate, forming a crystallization pattern by patterning the amorphous silicon film, and crystallizing the crystallization pattern into polycrystalline silicon by irradiating a laser onto the crystallization pattern. The crystallization pattern includes a peripheral region located within a first distance from an edge of the crystallization pattern, and an internal region located away from the edge of the crystallization pattern by more than the first distance. The internal region is divided into at least one sub-region, each sub-region includes one crystallization inducement pattern, and an edge of each sub-region is located within a second distance from the crystallization inducement pattern.
    Type: Application
    Filed: March 16, 2007
    Publication date: September 20, 2007
    Inventors: Myung Kwan Ryu, Eok Su Kim, Kyoung Seok Son, Jang Soon Im
  • Patent number: 7205033
    Abstract: Disclosed is a method for forming a polycrystalline silicon film of a polycrystalline silicon thin film transistor. The method includes a step of crystallizing an amorphous silicon film deposited on a glass substrate by irradiating a laser beam onto the amorphous silicon film using a mask pattern. The glass substrate is horizontally moved by a predetermined distance unit corresponding to a translation distance of the mask pattern when the laser beam is irradiated onto the amorphous silicon film through a mask having the mask pattern, thereby growing grains in a circular shape.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: April 17, 2007
    Assignee: Boe Hydis Technology Co., Ltd.
    Inventors: Eok Su Kim, Ho Nyeon Lee, Myung Kwan Ryu, Jae Chul Park, Kyoung Seok Son, Jun Ho Lee, Se Yeoul Kwon
  • Patent number: 7135388
    Abstract: The present invention relates to a method for fabricating a single crystal silicon thin film at the desired location to the desired size from an amorphous or polycrystalline thin film on a substrate using laser irradiation and laser beam movement along the substrate having the semiconductor thin films being irradiated. This method comprises the steps of: forming a semiconductor layer or a metal thin film on a transparent or semi-transparent substrate; forming a single crystal seed region on the substrate of the desired size by a crystallization method using laser irradiation; and converting the desired region of the semiconductor layer or metal thin film into a single crystal region, using the single crystal seed region.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: November 14, 2006
    Assignee: Boe Hydis Technology Co., Ltd.
    Inventors: Myung Kwan Ryu, Ho Nyeon Lee, Jae Chul Park, Eok Su Kim
  • Patent number: 7033915
    Abstract: Disclosed is a method for crystallizing a single crystalline Si film on an amorphous substrate, such as a glass substrate or a plastic substrate. The method includes the steps of selectively irradiating the laser beam onto a pixel section TFT forming region and a peripheral circuit TFT forming region of the amorphous silicon film through primary and secondary laser irradiation processes, thereby forming a poly-silicon film and irradiating the laser beam onto one of grains formed in the poly-silicon film through a third laser irradiation process, thereby forming a single crystalline silicon region having a desired size on a predetermined portion of the amorphous silicon film. The amorphous silicon film is locally crystallized into the single crystalline silicon film so that characteristics of TFTs for the pixel section and the peripheral circuit are improved while ensuring high uniformity.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: April 25, 2006
    Assignee: BOE Hydis Technology Co., Ltd.
    Inventors: Myung Kwan Ryu, Ho Nyeon Lee, Jae Chul Park, Eok Su Kim, Kyoung Seok Son, Jun Ho Lee, Se Yeoul Kwon