Abstract: A high capacity, secure and tamper-resistant computer data memory device. The device uses a plurality of dedicated memory controller elements in communication with an anti-tamper module that generates a tamper response when a predetermined tamper event occurs. The tamper response may be provided as the erasure or zeroization of the contents of a memory in the devices such as erasing one or more encryption keys. The elements of the device are preferably provided in a stacked configuration with rerouted I/O pads to obfuscate the I/O and function of the devices in the stack. In one embodiment, a data transfer governance means is provided. In a further embodiment, a current negotiation means is disclosed to permit the device to request a predetermined current from a host device. In a yet further embodiment, a portable safe house computing device is provided.

Abstract: A targeting sight having viewing optics, a focal plane array and an alignment frame having an aperture that defines a target area that is mounted proximal the muzzle of a weapon. Electronic processing means is provided to define a crosshair in the viewing optics. The alignment frame is illuminated with a beam and the reflected portion of the beam is received by the focal plane array and is processed to position the crosshair with respect to the aperture.

Abstract: A method for defining an electrically conductive metalized structure, which may comprise an electrode or trace, on the surface of a three-dimensional element. The three-dimensional element may comprise a glass microsphere or shell resonator. A laser direct write grayscale photolithographic process is used in conjunction with electrically conductive metal deposition processes to define one or more electrically conductive metal structures on the surfaces of the three dimensional element.

Abstract: A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.

Abstract: A process and product made from the process is disclosed to minimize solder collapse during solder reflow. Predetermined bond pads on a layer or component have a solder paste such as Sn63 solder paste with a first lower reflow temperature applied and a spacer element such as an SAC solder ball or stud bump having a predetermined geometry with a second higher reflow temperature applied. The SAC solder balls or stud bumps act as spacing elements but do not interact with the solder paste such that the solder paste may be reflowed while precisely maintaining the space between the layers.

Abstract: A method for providing a known good integrated circuit die having enhanced planarity from a prepackaged integrated circuit die having a surface warpage such as in a ball grid array (BGA) package is provided. A partially-depackaged integrated circuit package is affixed to a substrate with a spacer element there between such that the active surface of the die within the partially depackaged integrated circuit die is “bowed” slightly upwardly to define a convex surface. The exposed encapsulant on the now-convex surface of the mounted, partially-depackaged integrated circuit package is then lapped or ground away to a predetermined depth so that an integrated circuit die is provided having an enhanced planarity and surface uniformity.

Abstract: A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.

Abstract: A method and system for single-action personalized recommendation and display of content via the Internet. The recommendation is given by a server system and received by a client system. The content itself has been previously recommended to the server system by the users of the client system. Client system recommendations to the server system are also invoked with a single-action. Recommended content is referred to by a URL. Users can rate content to the server system using a single-action. The server system performs recommendation calculations using user-specific information such as user preferences, demographic data, content rating history, and content-specific information. The content rating history of other users may also influence these calculations. Client systems display recommended content directly to the user in response to only a single-action.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: A device and method using one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. The nano-structure is in connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the nano-structure is breached or altered. One or more electrically conductive nano-structures interconnect and reroute one or more electrical connections between one or more ICs to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device. microscope.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: In a preferred embodiment of the invention, a high density interconnect structure is provided comprised of a dielectric structure and one or more compressible conductive member for the electrical connection of a plurality of inputs and outputs of a three-dimensional module to external circuitry using a compression frame and a flex connector. The compression frame has a surface equal to or less than the surface area of the module surface upon which it is mounted and permits a plurality of modules to be “butted” together to provide, for instance, a buttable focal plane array module comprising a mosaic of buttable focal plane arrays.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: An energy-harvesting buoy is provided comprising an air-pressure generator, such as a piezo-electric generator, or any other generator that can harvest energy from an air pressure. The energy harvesting buoy consists of a first float and a second float. An air pressure is created when relative vertical motion occurs between the first float and the second float which drives an air pressurization means such as a piston driven air pump using a linkage member pivotably mounted between the respective floats. The generator uses the air pressure from the air pressurization means to drive the generator to generate electrical power.

Abstract: A device and method are disclosed comprising one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package (such as a TSOP, BGA or other prepackaged IC) a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. In one embodiment, the electrically conductive nano-structure is in electrical connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the electrically conductive nano-structure is breached or altered. The device may be configured to blow one or more fuses or overcurrent protection devices when the electrically conductive nano-structure is breached or altered.

Abstract: A sensing system is configured to detect physical parameters of a fluid sample. In particular, the sensing system is configured to detect the dew point of the fluid by reducing temperature of a sensing medium and detecting the fluid condensate on a sensing surface by directing light from a light source to the sensing surface and detecting the light reflected off the sensing surface onto a light detector. The light source and the light detector are on the opposite side of the sensing medium from the sensing surface.

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: A method for interconnecting stacked layers containing integrated circuit die and a device built from the method is disclosed. The stacked layers are bonded together to form a module whereby individual I/O pads of the integrated circuit die are rerouted to at least one edge of the module. The rerouted leads terminate at the edge. Channels are formed in a surface of the module or on the surface of a layer whereby the rerouted leads are disposed within the channel. The entire surface of the edge or layer is metalized and a predetermined portion of the metalization removed such that the rerouted leads within each channel are electrically connected to each other.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.