Patents by Inventor Eric Braun

Eric Braun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10705363
    Abstract: A privacy glazing structure may include an electrically controllable optically active material that provides controlled transition between a privacy or scattering state and a visible or transmittance state. To make electrical connections with electrode layers that control the optically active material, the privacy glazing structure may include electrode engagement regions. In some examples, the electrode engagement regions are formed as notches in peripheral edges of opposed panes bounding the optically active material. The notches may or may not overlap to provide a through conduit in the region of overlap for wiring. In either case, the notches may allow the remainder of the structure to have a flush edge surface for ease of downstream processing.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: July 7, 2020
    Assignee: Cardinal IG Company
    Inventors: Eric Berner, Eric Bjergaard, Timothy Braun, Andrew DeMiglio, Chad Peters
  • Patent number: 10665712
    Abstract: An LDMOS device with a field plate contact having a field plate contact metal layer being positioned above the field plate contact. The field plate contact metal layer has a sub-maximum size satisfied for the electrical connection between the field plate contact and an external applying voltage. This sub-maximum size is prescribed by the physical limitation of the LDMOS device. The field plate contact metal layer extends a sub-maximum length from one edge toward to the other edge of the field plate contact.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 26, 2020
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Eric Braun, Joel McGregor, Jeesung Jung
  • Publication number: 20200144381
    Abstract: An LDMOS device with a plurality of drain contact structures. Each drain contact structure has a drain contact, a first drain contact metal layer and a via. The drain contact is positioned above a drain region. The first drain contact metal layer is positioned above the drain contact. The via is positioned above the first drain contact metal layer. The LDMOS device has a second drain contact metal layer conductively coupled to the via of each drain contact structure.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 7, 2020
    Inventors: Eric Braun, Joel McGregor, Jeesung Jung
  • Publication number: 20200075760
    Abstract: An LDMOS device with a field plate contact having a field plate contact metal layer being positioned above the field plate contact. The field plate contact metal layer has a sub-maximum size satisfied for the electrical connection between the field plate contact and an external applying voltage. This sub-maximum size is prescribed by the physical limitation of the LDMOS device. The field plate contact metal layer extends a sub-maximum length from one edge toward to the other edge of the field plate contact.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Inventors: Eric Braun, Joel McGregor, Jeesung Jung
  • Publication number: 20200039341
    Abstract: A drive train includes a first gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a second gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a first motor/generator coupled to the first gear set, a second motor/generator coupled to the second gear set, a first clutch that selectively engages the second motor/generator with the first gear set, and a second clutch that selectively engages the ring gear of the second gear set with the planetary gear carrier of at least one of the first gear set and the second gear set. The planetary gears of both sets are rotatably supported by respective planetary gear carriers.
    Type: Application
    Filed: October 3, 2019
    Publication date: February 6, 2020
    Applicant: Oshkosh Defense, LLC
    Inventors: Jon Morrow, Dave Steinberger, Eric Braun, Andrew Kotloski, Nader Nasr
  • Publication number: 20200020032
    Abstract: A system and method that relies upon smart contracts to facilitate cryptocurrency trades through a plurality of different exchanges. The system and method preferably operate on the blockchain.
    Type: Application
    Filed: July 14, 2019
    Publication date: January 16, 2020
    Inventors: David BLEZNAK, Sergey TSYBA, Jordan LYALL, Noah PASSALACQUA, Nate WELCH, Craig BRAUN, Ed POSNAK, Eric BUJOLD, Colleen STABLER, Svenn MAHLE, Katie HORNE, Austin ROBERTS, Chris BEHAR, Andrew TRUDEL, Andrew KATSEVICH, Harry WRIGHT, Audrey SCIORTINO
  • Patent number: 10457134
    Abstract: A drive train includes a shaft, a first gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a second gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a first motor/generator coupled to the first gear set, a second motor/generator coupled to the second gear set, a first clutch that selectively engages the shaft with the second motor/generator and the first gear set, and a second clutch and a third gear set that cooperate to selectively engage the ring gear of the second gear set with the planetary gear carrier of at least one of the first gear set and the second gear set. The planetary gears of both sets are rotatably supported by respective planetary gear carriers.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 29, 2019
    Assignee: Oshkosh Defense, LLC
    Inventors: Jon Morrow, Dave Steinberger, Eric Braun, Andrew Kotloski, Nader Nasr
  • Patent number: 10263420
    Abstract: An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate and the body of the discharging transistor are electrically coupled together. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: April 16, 2019
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Eric Braun
  • Publication number: 20190088641
    Abstract: An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate of the discharging transistor is electrically coupled to a driving voltage. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Inventor: Eric Braun
  • Publication number: 20180345783
    Abstract: A drive train includes a shaft, a first gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a second gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a first motor/generator coupled to the first gear set, a second motor/generator coupled to the second gear set, a first clutch that selectively engages the shaft with the second motor/generator and the first gear set, and a second clutch and a third gear set that cooperate to selectively engage the ring gear of the second gear set with the planetary gear carrier of at least one of the first gear set and the second gear set. The planetary gears of both sets are rotatably supported by respective planetary gear carriers.
    Type: Application
    Filed: July 23, 2018
    Publication date: December 6, 2018
    Applicant: Oshkosh Defense, LLC
    Inventors: Jon Morrow, Dave Steinberger, Eric Braun, Andrew Kotloski, Nader Nasr
  • Publication number: 20180286857
    Abstract: A semiconductor device having a dummy trench structure. The dummy trench structure vertically extends from the top surface of the semiconductor device through a body region into a semiconductor initial layer, and the body region separates the dummy trench structure from a source region. The dummy trench structure has a trench dielectric and a trench conductive material. The semiconductor initial layer, the trench dielectric and the trench conductive material are served as a capacitor of an integrated snubber of the semiconductor device, and the trench conductive material is served as a resistor of the snubber.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 4, 2018
    Inventors: Huaifeng Wang, Eric Braun, Ling Wang
  • Patent number: 10083930
    Abstract: A semiconductor device reducing parasitic loop inductance of system for the switching converter. The semiconductor device has an input voltage pin, a ground reference pin, a switching pin, and a semiconductor die, wherein the semiconductor die comprises a high-side power switch and a low-side power switch and a metal connection. The metal connection directly connects the high-side power switch and the first terminal of the low-side power switch, and is along and proximity to an edge of the semiconductor device to which the input voltage pin is distributed.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: September 25, 2018
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Huaifeng Wang, Eric Braun, Hunt Hang Jiang, Francis Yu
  • Patent number: 10069422
    Abstract: A synchronous switching converter has an integrated semiconductor device. The integrated semiconductor device has a first semiconductor component and a second semiconductor component coupled in parallel. The first semiconductor component has MOSFET cells with body diodes, and the second semiconductor component has diode cells or MOSFET cells with a low forward voltage. Cells of the second semiconductor component distribute among the first semiconductor component unevenly according to a distribution of a current flowing through the integrated semiconductor device.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: September 4, 2018
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Huaifeng Wang, Eric Braun
  • Patent number: 10029556
    Abstract: A drive train for a vehicle includes an engine having an output shaft, a first gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a second gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a first motor/generator coupled to the first gear set, a second motor/generator coupled to the second gear set and electrically coupled to the first motor/generator, a first clutch that selectively engages the output shaft of the engine with the second motor/generator, and a second clutch and a third gear set that cooperate to selectively engage the ring gear of the second gear set with the planetary gear carrier of at least one of the first gear set and the second gear set.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 24, 2018
    Assignee: Oshkosh Defense, LLC
    Inventors: Jon Morrow, Dave Steinberger, Eric Braun, Andrew Kotloski, Nader Nasr
  • Patent number: 9892787
    Abstract: A multi-time programmable memory cell has a differential multi-time programmable memory cell and a second-level latch cell. The differential multi-time programmable memory cell provides a first balance signal and a second balance signal, and the second-level latch cell receives the first balance signal and the second balance signal and provides an output signal according to the first balance signal and the second balance signal based on a first latch control signal and a second latch control signal.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: February 13, 2018
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Da Chen, Eric Braun
  • Patent number: 9893146
    Abstract: A lateral DMOS device with peak electric field moved below a top surface of the device along a body-drain junction is introduced. The LDMOS has a deep body and a drift region formed by a series of P-type and N-type implants, respectively. The implant doses and depths are tuned so that the highest concentration gradient of the body-drift junction is formed below the surface, which suppresses the injection and trapping of hot holes in the device drain-gate oxide region vicinity, and the associated device performance changes, during operation in breakdown.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: February 13, 2018
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Eric Braun, Joel McGregor, Jeesung Jung, Ji-Hyoung Yoo
  • Patent number: 9893518
    Abstract: An ESD protection circuit used to protect a protected circuit coupled between a first node and a second node against an ESD event. The ESD protection circuit has a discharging circuit and a control circuit. The discharging circuit selectively provides a current path for discharging a current from the first node to the second node. The control circuit controls the discharging circuit to switch on the current path during an ESD event. The control circuit further controls the discharging circuit to switch off the current path during the normal operation of the protected circuit.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: February 13, 2018
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Eric Braun
  • Publication number: 20170287559
    Abstract: A multi-time programmable memory cell has a differential multi-time programmable memory cell and a second-level latch cell. The differential multi-time programmable memory cell provides a first balance signal and a second balance signal, and the second-level latch cell receives the first balance signal and the second balance signal and provides an output signal according to the first balance signal and the second balance signal based on a first latch control signal and a second latch control signal.
    Type: Application
    Filed: March 22, 2017
    Publication date: October 5, 2017
    Inventors: Da Chen, Eric Braun
  • Publication number: 20170256940
    Abstract: An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate and the body of the discharging transistor are electrically coupled together. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 7, 2017
    Inventor: Eric Braun
  • Patent number: D859488
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: September 10, 2019
    Assignee: Charles River Laboratories, Inc.
    Inventors: Jason Tremblay, Dana M. Nutter, Elizabeth Mills, Luca Nicoli, Eric Stimpson, Thomas Preidel, Michael Braun