Abstract: An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate and the body of the discharging transistor are electrically coupled together. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.

Abstract: An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate of the discharging transistor is electrically coupled to a driving voltage. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.

Abstract: A drive train includes a shaft, a first gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a second gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a first motor/generator coupled to the first gear set, a second motor/generator coupled to the second gear set, a first clutch that selectively engages the shaft with the second motor/generator and the first gear set, and a second clutch and a third gear set that cooperate to selectively engage the ring gear of the second gear set with the planetary gear carrier of at least one of the first gear set and the second gear set. The planetary gears of both sets are rotatably supported by respective planetary gear carriers.

Abstract: A semiconductor device having a dummy trench structure. The dummy trench structure vertically extends from the top surface of the semiconductor device through a body region into a semiconductor initial layer, and the body region separates the dummy trench structure from a source region. The dummy trench structure has a trench dielectric and a trench conductive material. The semiconductor initial layer, the trench dielectric and the trench conductive material are served as a capacitor of an integrated snubber of the semiconductor device, and the trench conductive material is served as a resistor of the snubber.

Abstract: A semiconductor device reducing parasitic loop inductance of system for the switching converter. The semiconductor device has an input voltage pin, a ground reference pin, a switching pin, and a semiconductor die, wherein the semiconductor die comprises a high-side power switch and a low-side power switch and a metal connection. The metal connection directly connects the high-side power switch and the first terminal of the low-side power switch, and is along and proximity to an edge of the semiconductor device to which the input voltage pin is distributed.

Abstract: A synchronous switching converter has an integrated semiconductor device. The integrated semiconductor device has a first semiconductor component and a second semiconductor component coupled in parallel. The first semiconductor component has MOSFET cells with body diodes, and the second semiconductor component has diode cells or MOSFET cells with a low forward voltage. Cells of the second semiconductor component distribute among the first semiconductor component unevenly according to a distribution of a current flowing through the integrated semiconductor device.

Abstract: A drive train for a vehicle includes an engine having an output shaft, a first gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a second gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a first motor/generator coupled to the first gear set, a second motor/generator coupled to the second gear set and electrically coupled to the first motor/generator, a first clutch that selectively engages the output shaft of the engine with the second motor/generator, and a second clutch and a third gear set that cooperate to selectively engage the ring gear of the second gear set with the planetary gear carrier of at least one of the first gear set and the second gear set.

Abstract: A multi-time programmable memory cell has a differential multi-time programmable memory cell and a second-level latch cell. The differential multi-time programmable memory cell provides a first balance signal and a second balance signal, and the second-level latch cell receives the first balance signal and the second balance signal and provides an output signal according to the first balance signal and the second balance signal based on a first latch control signal and a second latch control signal.

Abstract: A lateral DMOS device with peak electric field moved below a top surface of the device along a body-drain junction is introduced. The LDMOS has a deep body and a drift region formed by a series of P-type and N-type implants, respectively. The implant doses and depths are tuned so that the highest concentration gradient of the body-drift junction is formed below the surface, which suppresses the injection and trapping of hot holes in the device drain-gate oxide region vicinity, and the associated device performance changes, during operation in breakdown.

Abstract: An ESD protection circuit used to protect a protected circuit coupled between a first node and a second node against an ESD event. The ESD protection circuit has a discharging circuit and a control circuit. The discharging circuit selectively provides a current path for discharging a current from the first node to the second node. The control circuit controls the discharging circuit to switch on the current path during an ESD event. The control circuit further controls the discharging circuit to switch off the current path during the normal operation of the protected circuit.

Abstract: A multi-time programmable memory cell has a differential multi-time programmable memory cell and a second-level latch cell. The differential multi-time programmable memory cell provides a first balance signal and a second balance signal, and the second-level latch cell receives the first balance signal and the second balance signal and provides an output signal according to the first balance signal and the second balance signal based on a first latch control signal and a second latch control signal.

Abstract: A synchronous switching converter has an integrated semiconductor device. The integrated semiconductor device has a first semiconductor component and a second semiconductor component coupled in parallel. The first semiconductor component has MOSFET cells with body diodes, and the second semiconductor component has diode cells or MOSFET cells with a low forward voltage. Cells of the second semiconductor component distribute among the first semiconductor component unevenly according to a distribution of a current flowing through the integrated semiconductor device.

Abstract: An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate and the body of the discharging transistor are electrically coupled together. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.

Abstract: A semiconductor device reducing parasitic loop inductance of system for the switching converter. The semiconductor device has an input voltage pin, a ground reference pin, a switching pin, and a semiconductor die, wherein the semiconductor die comprises a high-side power switch and a low-side power switch and a metal connection. The metal connection directly connects the high-side power switch and the first terminal of the low-side power switch, and is along and proximity to an edge of the semiconductor device to which the input voltage pin is distributed.

Abstract: An ESD protection circuit used to protect a protected circuit coupled between a first node and a second node against an ESD event. The ESD protection circuit has a discharging circuit and a control circuit. The discharging circuit selectively provides a current path for discharging a current from the first node to the second node. The control circuit controls the discharging circuit to switch on the current path during an ESD event. The control circuit further controls the discharging circuit to switch off the current path during the normal operation of the protected circuit.

Abstract: A switching circuit having a low side driver providing a three-level low side drive signal keeps a low side power switch slightly on during a dead time between the low side power switch turn off and a high side power switch turn on, thus a current flowing through a body diode is mostly distributed to the slightly on low side power switch instead of the body diode.

Abstract: A drive train for a vehicle includes an engine having an output shaft, a first gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a second gear set including a sun gear, a ring gear and planetary gears coupling the sun gear to the ring gear, a first motor/generator coupled to the first gear set, a second motor/generator coupled to the second gear set and electrically coupled to the first motor/generator, a first clutch that selectively engages the output shaft of the engine with the second motor/generator, and a second clutch and a third gear set that cooperate to selectively engage the ring gear of the second gear set with the planetary gear carrier of at least one of the first gear set and the second gear set.

Abstract: An EEPROM memory cell with a coupler region is disclosed. The coupler region has a well and at least one feeder region formed in the well. The at least one feeder region is configured to provide majority carriers to a channel region defined in the well so that a portion of the channel region adjoining the top surface of the coupler region is inverted during an erase operation.

Abstract: A drive train for a vehicle includes an engine having an output shaft, a first gear set, a second gear set, a first motor/generator coupled to the first gear set, a second motor/generator coupled to the second gear set and electrically coupled to the first motor/generator, a first clutch, and a second clutch. Planetary gears of both sets are rotatably supported by respective planetary gear carriers that are coupled to each other. The first clutch selectively engages the output shaft of the engine with the second motor/generator, and the second clutch and a third gear set operate to selectively engage at least one of the sun gear and the ring gear of the second gear set with the planetary gear carriers of the first and second gear sets.

Abstract: An OTP memory cell and an OTP memory circuit. The OTP memory cell having a memory module, a write module, a read module, and a load module. Data may be written into the memory module once the write module is active; and data may be read out of the memory module once the read module is active. The OTP memory cell may also have a first latch module and a second latch module.