Patents by Inventor Eric J. Shero

Eric J. Shero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7569284
    Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: August 4, 2009
    Assignee: ASM America, Inc.
    Inventors: Eric J Shero, Christophe Pomarede
  • Patent number: 7476627
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: January 13, 2009
    Assignee: ASM America, Inc.
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero
  • Publication number: 20080286589
    Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.
    Type: Application
    Filed: July 3, 2008
    Publication date: November 20, 2008
    Applicant: ASM AMERICA, INC.
    Inventors: Eric J. Shero, Christophe Pomarede
  • Patent number: 7405453
    Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: July 29, 2008
    Assignee: ASM America, Inc.
    Inventors: Eric J. Shero, Christophe Pomarede
  • Publication number: 20080020593
    Abstract: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a metal source chemical, a silicon source chemical and an oxidizing agent. In preferred embodiments, an alkyl amide metal compound and a silicon halide compound are used. Methods according to preferred embodiments can be used to form hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surfaces comprising high aspect ratio features (e.g., vias and/or trenches).
    Type: Application
    Filed: July 21, 2006
    Publication date: January 24, 2008
    Inventors: Chang-gong Wang, Eric J. Shero, Glen Wilk, Jan Willem Maes
  • Patent number: 7122085
    Abstract: Preferred embodiments of the present invention provides a sublimation system employing guidance structures including certain preferred embodiments having a high surface area support medium onto which a solid source material for vapor reactant is coated. Preferably, a guidance structure is configured to facilitate the repeated saturation of the carrier gas with the solid source for a vapor reactant. Methods of saturating a carrier gas using guidance structures are also provided.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: October 17, 2006
    Assignee: ASM America, Inc.
    Inventors: Eric J. Shero, Michael E. Givens, Ryan Schmidt
  • Patent number: 7118779
    Abstract: Protective layers are formed on a surface of an atomic layer deposition (ALD) or chemical vapor deposition (CVD) reactor. Parts defining a reaction space for an ALD or CVD reactor can be treated, in situ or ex situ, with chemicals that deactivate reactive sites on the reaction space surface(s). A pre-treatment step can maximize the available reactive sites prior to the treatment step. With reactive sites deactivated by adsorbed treatment reactant, during subsequent processing the reactant gases have reduced reactivity or deposition upon these treated surfaces. Accordingly, purge steps can be greatly shortened and a greater number of runs can be conducted between cleaning steps to remove built-up deposition on the reactor walls.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: October 10, 2006
    Assignee: ASM America, Inc.
    Inventors: Mohith Verghese, Eric J. Shero
  • Patent number: 7056835
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: June 6, 2006
    Assignee: ASM America, Inc.
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero
  • Patent number: 7026219
    Abstract: Methods are provided herein for forming electrode layers over high dielectric constant (“high k”) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes aid in reducing hydrogen content for a given deposition rate.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: April 11, 2006
    Assignee: ASM America, Inc.
    Inventors: Christophe F. Pomarede, Michael E. Givens, Eric J. Shero, Michael A. Todd
  • Patent number: 7022613
    Abstract: In accordance with one aspect of the present invention, a method is provided for transporting a workpiece in a semiconductor processing apparatus comprising a transfer chamber, a process chamber, and a gate valve between the transfer chamber and the process chamber. The method comprises vacuum pumping the transfer chamber to achieve a first pressure in the transfer chamber and vacuum pumping the process chamber to achieve a second pressure in the process chamber. An inert gas is flowed into the transfer chamber and shut off in the process chamber. The transfer chamber is isolated from pumping, but pumping continues from the process chamber. The gate valve is opened after isolating the transfer chamber from pumping. The workpiece is then transferred between the transfer chamber and the process chamber. A definitive flow direction from transfer chamber to process chamber is thereby achieved, minimizing risk of back-diffusion.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: April 4, 2006
    Assignee: ASM America, Inc.
    Inventors: Christophe Pomarede, Eric J. Shero, Olli Jylhä
  • Patent number: 7020981
    Abstract: A reactor defines a reaction chamber for processing a substrate. The reactor comprises a first inlet for providing a first reactant and to the reaction chamber and a second inlet for a second reactant to the reaction chamber. A first exhaust outlet removes gases from the reaction chamber. A second exhaust outlet removes gases from the reaction chamber. A flow control system is configured to alternately constrict flow through the first and second exhaust outlets. The reactor chamber is configured to for a diffusion barrier within the reaction chamber.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: April 4, 2006
    Assignee: ASM America, INC
    Inventors: Eric J. Shero, Mohith E. Verghese
  • Patent number: 6960537
    Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: November 1, 2005
    Assignee: ASM America, Inc.
    Inventors: Eric J. Shero, Christophe Pomarede
  • Patent number: 6958277
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: October 25, 2005
    Assignee: ASM America, Inc.
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero
  • Publication number: 20040221807
    Abstract: Protective layers are formed on a surface of an atomic layer deposition (ALD) or chemical vapor deposition (CVD) reactor. Parts defining a reaction space for an ALD or CVD reactor can be treated, in situ or ex situ, with chemicals that deactivate reactive sites on the reaction space surface(s). A pre-treatment step can maximize the available reactive sites prior to the treatment step. With reactive sites deactivated by adsorbed treatment reactant, during subsequent processing the reactant gases have reduced reactivity or deposition upon these treated surfaces. Accordingly, purge steps can be greatly shortened and a greater number of runs can be conducted between cleaning steps to remove built-up deposition on the reactor walls.
    Type: Application
    Filed: May 7, 2004
    Publication date: November 11, 2004
    Inventors: Mohith Verghese, Eric J. Shero
  • Patent number: 6797617
    Abstract: In accordance with one aspect of the present invention, a method is provided for transporting a workpiece in a semiconductor processing apparatus comprising a transfer chamber, a process chamber, and a gate valve between the transfer chamber and the process chamber. The method comprises vacuum pumping the transfer chamber to achieve a first pressure in the transfer chamber and vacuum pumping the process chamber to achieve a second pressure in the process chamber. An inert gas is flowed into the transfer chamber and shut off in the process chamber. The transfer chamber is isolated from pumping, but pumping continues from the process chamber. The gate valve is opened after isolating the transfer chamber from pumping. The workpiece is then transferred between the transfer chamber and the process chamber. A definitive flow direction from transfer chamber to process chamber is thereby achieved, minimizing risk of back-diffusion.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: September 28, 2004
    Assignee: ASM America, Inc.
    Inventors: Christophe Pomarede, Eric J. Shero, Olli Jylhä
  • Publication number: 20040166683
    Abstract: In accordance with one aspect of the present invention, a method is provided for transporting a workpiece in a semiconductor processing apparatus comprising a transfer chamber, a process chamber, and a gate valve between the transfer chamber and the process chamber. The method comprises vacuum pumping the transfer chamber to achieve a first pressure in the transfer chamber and vacuum pumping the process chamber to achieve a second pressure in the process chamber. An inert gas is flowed into the transfer chamber and shut off in the process chamber. The transfer chamber is isolated from pumping, but pumping continues from the process chamber. The gate valve is opened after isolating the transfer chamber from pumping. The workpiece is then transferred between the transfer chamber and the process chamber. A definitive flow direction from transfer chamber to process chamber is thereby achieved, minimizing risk of back-diffusion.
    Type: Application
    Filed: February 24, 2004
    Publication date: August 26, 2004
    Inventors: Christophe Pomarede, Eric J. Shero, Olli Jylha
  • Publication number: 20040147101
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Application
    Filed: July 24, 2003
    Publication date: July 29, 2004
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero
  • Publication number: 20040121620
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Application
    Filed: July 24, 2003
    Publication date: June 24, 2004
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero
  • Publication number: 20030219977
    Abstract: In accordance with one aspect of the present invention, a method is provided for transporting a workpiece in a semiconductor processing apparatus comprising a transfer chamber, a process chamber, and a gate valve between the transfer chamber and the process chamber. The method comprises vacuum pumping the transfer chamber to achieve a first pressure in the transfer chamber and vacuum pumping the process chamber to achieve a second pressure in the process chamber. An inert gas is flowed into the transfer chamber and shut off in the process chamber. The transfer chamber is isolated from pumping, but pumping continues from the process chamber. The gate valve is opened after isolating the transfer chamber from pumping. The workpiece is then transferred between the transfer chamber and the process chamber. A definitive flow direction from transfer chamber to process chamber is thereby achieved, minimizing risk of back-diffusion.
    Type: Application
    Filed: May 20, 2003
    Publication date: November 27, 2003
    Inventors: Christophe Pomarede, Eric J. Shero, Olli Jylha
  • Patent number: 6613695
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: September 2, 2003
    Assignee: ASM America, Inc.
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero