Patents by Inventor Eric J. Shero

Eric J. Shero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030072975
    Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.
    Type: Application
    Filed: September 26, 2002
    Publication date: April 17, 2003
    Inventors: Eric J. Shero, Christophe Pomarede
  • Publication number: 20020173130
    Abstract: Methods are provided herein for forming electrode layers over high dielectric constant (high k) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes aid in reducing hydrogen content for a given deposition rate.
    Type: Application
    Filed: February 11, 2002
    Publication date: November 21, 2002
    Inventors: Christophe F. Pomerede , Michael E. Givens , Eric J. Shero , Michael A. Todd
  • Publication number: 20020098627
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Application
    Filed: August 31, 2001
    Publication date: July 25, 2002
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero
  • Patent number: 5145924
    Abstract: High molecular weight polymers of vinyl aromatic monomers are prepared by free radical polymerization in the presence of 5 to 5000 ppm of a soluble organic acid having pKa from 0.5 to 2.5.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: September 8, 1992
    Assignee: The Dow Chemical Company
    Inventors: Eric J. Shero, James J. O'Brien, Duane B. Priddy