Patents by Inventor Eric M. Rentschler

Eric M. Rentschler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7103793
    Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: September 5, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Eric M. Rentschler, Jeffrey G. Hargis, George T. Letey, Leith L. Johnson
  • Patent number: 6990562
    Abstract: A memory controller is provided with a memory to store indications of data/strobe ratios that are required to access memory devices that are coupled to the memory controller. The memory controller is also provided with a memory interface through which the memory controller initiates data transmissions with the memory devices. For a data transmission initiated with a particular one of the memory devices, the ratio of data signals to strobe signals sent/received through the interface is dynamically determined in response to a corresponding indication of a data/strobe ratio stored in the memory.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: January 24, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Eric M. Rentschler, Jeffrey G. Hargis, George T. Letey
  • Patent number: 6889335
    Abstract: Methods and apparatus are disclosed herein for providing tri-state noise immunity for memory systems such as DDR memory systems, wherein 1) there are large variations in read data loop delay, and 2) strobe buses have similar termination and threshold voltages. In one embodiment, strobe receiver circuitry includes a counter and counter control logic. The counter updates a count in response to strobe edges of received strobe signals. The counter control logic enables the counter before each strobe signal is received by generating control signals asynchronously with respect to the received strobe signals. The counter control logic also resets the counter after each strobe signal is received by receiving feedback from the counter and, in response to the feedback, resetting the counter asynchronously with respect to the received strobe signals. The strobe receiver circuitry may form part of a DDR memory controller.
    Type: Grant
    Filed: April 7, 2001
    Date of Patent: May 3, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeffrey G. Hargis, Eric M. Rentschler, Leith L. Johnson
  • Publication number: 20040158688
    Abstract: A memory controller is provided with a memory to store indications of data/strobe ratios that are required to access memory devices that are coupled to the memory controller. The memory controller is also provided with a memory interface through which the memory controller initiates data transmissions with the memory devices. For a data transmission initiated with a particular one of the memory devices, the ratio of data signals to strobe signals sent/received through the interface is dynamically determined in response to a corresponding indication of a data/strobe ratio stored in the memory.
    Type: Application
    Filed: October 14, 2003
    Publication date: August 12, 2004
    Inventors: Eric M. Rentschler, Jeffrey G. Hargis, George T. Letey
  • Publication number: 20040133757
    Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).
    Type: Application
    Filed: October 14, 2003
    Publication date: July 8, 2004
    Inventors: Eric M. Rentschler, Jeffrey G. Hargis, George T. Letey, Leith L. Johnson
  • Publication number: 20040088512
    Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means for receiving data and strobe signals via said pads at M× double data rate memory speed (M≧2).
    Type: Application
    Filed: October 28, 2003
    Publication date: May 6, 2004
    Inventors: Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson
  • Patent number: 6678811
    Abstract: Methods and apparatus for writing data to memory are disclosed herein. In general, the methods and apparatus provide a memory controller with means for writing data at different rates. Data may need to be written to memory at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, comprise demultiplexers which receive data from the memory controller at twice the rate which data could be written directly to a memory module. The intermediary chip may then simultaneously transmit the demultiplexed write data to memory modules in two or more banks of memory modules.
    Type: Grant
    Filed: April 7, 2001
    Date of Patent: January 13, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson
  • Publication number: 20030221059
    Abstract: A fully mirrored memory system includes at least one split memory bus, with each portion of the split memory bus having active memory and mirror memory. Each portion of the memory bus transfers a portion of the data for a memory transaction. If a memory unit is determined to be defective, one portion of the memory bus may be inactivated for hot swapping of memory, and the system can continue to operate using an active portion of the memory bus.
    Type: Application
    Filed: May 22, 2002
    Publication date: November 27, 2003
    Inventors: Darel N. Emmot, Eric M. Rentschler
  • Publication number: 20030221058
    Abstract: A fully mirrored memory system includes mirror memory on the same memory bus as the active memory. Data is written to both active memory and mirror memory. Select-signal lines are used to control which memory units are used for writing and reading. If a memory unit is determined to be defective, the signal-select lines are used to logically replace the active memory unit with its corresponding mirror memory unit for reading.
    Type: Application
    Filed: May 22, 2002
    Publication date: November 27, 2003
    Inventors: Eric M. Rentschler, Michael Kennard Tayler
  • Patent number: 6633965
    Abstract: Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.
    Type: Grant
    Filed: April 7, 2001
    Date of Patent: October 14, 2003
    Inventors: Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson
  • Patent number: 6625702
    Abstract: A memory controller that reads and writes memory modules populated with non-homogeneous data width RAM devices, wherein the RAM devices are of a type which send and receive data with a source synchronous strobe. The memory controller maintains a memory map and stores therein indications of data/strobe ratios which are required to read and write memory modules coupled to the memory controller. The indications of data/strobe ratios are addressed during read and write cycles of the memory controller. Addressed indications are used during write cycles to ensure that strobes are generated at a correct number of strobe pads. Addressed indications are used during read cycles to ensure that received data signals are associated with their correct and corresponding strobe signals.
    Type: Grant
    Filed: April 7, 2001
    Date of Patent: September 23, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Eric M. Rentschler, Jeffrey G. Hargis, George T Letey
  • Publication number: 20020172079
    Abstract: Methods and apparatus are disclosed herein for providing tri-state noise immunity for memory systems such as DDR memory systems, wherein 1) there are large variations in read data loop delay, and 2) strobe buses have similar termination and threshold voltages. In one embodiment, strobe receiver circuitry includes a counter and counter control logic. The counter updates a count in response to strobe edges of received strobe signals. The counter control logic enables the counter before each strobe signal is received by generating control signals asynchronously with respect to the received strobe signals. The counter control logic also resets the counter after each strobe signal is received by receiving feedback from the counter and, in response to the feedback, resetting the counter asynchronously with respect to the received strobe signals. The strobe receiver circuitry may form part of a DDR memory controller.
    Type: Application
    Filed: April 7, 2001
    Publication date: November 21, 2002
    Inventors: Jeffrey G. Hargis, Eric M. Rentschler, Leith L. Johnson
  • Publication number: 20020147898
    Abstract: A memory controller that reads and writes memory modules populated with non-homogeneous data width RAM devices, wherein the RAM devices are of a type which send and receive data with a source synchronous strobe. The memory controller maintains a memory map and stores therein indications of data/strobe ratios which are required to read and write memory modules coupled to the memory controller. The indications of data/strobe ratios are addressed during read and write cycles of the memory controller. Addressed indications are used during write cycles to ensure that strobes are generated at a correct number of strobe pads. Addressed indications are used during read cycles to ensure that received data signals are associated with their correct and corresponding strobe signals.
    Type: Application
    Filed: April 7, 2001
    Publication date: October 10, 2002
    Inventors: Eric M. Rentschler, Jeffrey G. Hargis, George T. Letey
  • Publication number: 20020147896
    Abstract: Methods and apparatus for writing data to memory are disclosed herein. In general, the methods and apparatus provide a memory controller with means for writing data at different rates. Data may need to be written to memory at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, comprise demultiplexers which receive data from the memory controller at twice the rate which data could be written directly to a memory module. The intermediary chip may then simultaneously transmit the demultiplexed write data to memory modules in two or more banks of memory modules.
    Type: Application
    Filed: April 7, 2001
    Publication date: October 10, 2002
    Inventors: Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson
  • Publication number: 20020147892
    Abstract: Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.
    Type: Application
    Filed: April 7, 2001
    Publication date: October 10, 2002
    Inventors: Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson
  • Patent number: 6381663
    Abstract: An apparatus and method for permitting bus locking in a computer system having a mixed architecture. The mixed architecture includes a first bus coupled to processors that may run applications using bus locking or cache line locking. The apparatus interfaces the first bus with a second bus that does not support bus locking. The apparatus when presented with a locked transaction effectively implements bus locking on the second bus.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: April 30, 2002
    Assignee: Hewlett-Packard Company
    Inventors: John A. Morrison, Robert J. Blakely, Eric M. Rentschler, John R. Feehrer
  • Publication number: 20020038398
    Abstract: An apparatus and method for permitting bus locking in a computer system having a mixed architecture. The mixed architecture includes a first bus coupled to processors that may run applications using bus locking or cache line locking. The apparatus interfaces the first bus with a second bus that does not support bus locking. The apparatus when presented with a locked transaction effectively implements bus locking on the second bus.
    Type: Application
    Filed: March 26, 1999
    Publication date: March 28, 2002
    Inventors: JOHN A. MORRISON, ROBERT J. BLAKELY, ERIC M. RENTSCHLER, JOHN R. FEEHRER
  • Patent number: 6360301
    Abstract: A lower level cache detects when a line of memory has been evicted from a higher level cache. The cache coherency protocol for the lower level cache places the line into a special state. If a line in the special state is evicted from the lower level cache, the lower level cache knows that the line is not cached at a higher level, and therefore a back-invalidate transaction is not needed. Reducing the number of back-invalidate transactions improves the performance of the system.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: March 19, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Blaine D Gaither, Eric M Rentschler
  • Patent number: 5969726
    Abstract: A computer graphics system for rendering graphics primitives based upon primitive data received from a host computer through a graphics interface includes a plurality of geometry accelerators. A distributor divides the primitive data into chunks of primitive data and distributes the chunks to a current geometry accelerator recipient. A state controller is configured to store and resend selected primitive data to the geometry accelerators based upon whether one or more vertices of a graphics primitive are contained in more than one of the chunks of primitive data. Advantageously, this enables the computer graphics system to efficiently process primitive data while avoiding providing the geometry accelerators with an excessive amount of data than necessary for them to render the primitives.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: October 19, 1999
    Assignee: Hewlett-Packard Co.
    Inventors: Eric M. Rentschler, Alan S. Krech, Jr.
  • Patent number: 5821950
    Abstract: A computer graphics system includes a plurality of geometry accelerators for processing vertex data representative of graphics primitives and providing rendering data. The system includes a distributor responsive to a stream of vertex data for distributing to the geometry accelerators chunks of the vertex data for processing by the geometry accelerators to provide chunks of rendering data. The distributor generates an end of chunk bit indicative of the end of each of the chunks of vertex data. The system further includes a concentrator for receiving the chunks of rendering data from each of the geometry accelerators and for combining the chunks of rendering data into a stream of rendering data in response to end of chunk bits. The stream of rendering data and the stream of vertex data represent sequences of graphics primitives having the same order. A rasterizer generates pixel data representative of a graphics display in response to the stream of rendering data.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: October 13, 1998
    Assignee: Hewlett-Packard Company
    Inventors: Eric M. Rentschler, Monish S. Shah, Mary A. Matthews, Alan S. Krech, Jr., Erin A. Handgen