Abstract: The disclosure relates to chemokine CXCR4 receptor modulators and uses related thereto. The receptor modulators can be formulated to form pharmaceutical compositions comprising the disclosed compounds or pharmaceutically acceptable salts or prodrugs thereof. The compositions may be used for managing CXCR4 related conditions, typically prevention or treatment of viral infections abnormal cellular proliferation, retinal degeneration, inflammatory diseases, or as an immunostimulant or immunosuppressant or for managing cancer and may be administered with another active ingredient such as an antiviral agent or chemotherapeutic agent.

Abstract: An electrical device includes a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The dielectric layer may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer to facilitate 3D-integration.

Abstract: A semiconductor structure includes a substrate and a gate-all-around field effect transistor disposed over the substrate. The gate-all-around field effect transistor includes a first source-drain region; a second source-drain region; at least one channel region interconnecting the first and second source drain regions; and a gate structure surrounding the at least one channel region. A self-aligned substrate isolation (SASI) layer is located between the substrate and the gate structure and extends over a width of the gate structure.

Abstract: A semiconductor device is provided that includes a transistor in which a self-aligned backside dielectric structure is in contact with one of the source/drain regions of the transistors and a self-aligned backside source/drain contact structure is in electrical contact with the other source/drain region of the transistor.

Abstract: A blender system that includes a base that is selectively and operatively engaged with a container that is shown and described herein. The base may include a near field communications chip that may communicate with a near field communications chip of a container. The base also includes a motor that is selectively and operatively engaged with a blade disposed within a container.

Abstract: A semiconductor device including a first nanodevice is located on a substrate, where the first nanodevice includes at least one channel. A first source/drain connected to the first nanodevice. A second nanodevice located on the substrate, where the second nanodevice includes at least one channel and a second source/drain connected to the second nanodevice. A first contact located above the first source/drain. A second contact located above the second source/drain. A contact cap located on top of the first contact and the second contact, where the contact cap has a first leg that extends downwards between the first contact and the second contact. The first leg of the contact cap is in contact with a first sidewall of the first contact, and a first sidewall of the second contact.

Abstract: An electrical terminal includes a body with a first opening for receiving an electrical conductor and a second opening for coupling the electrical terminal to an electrically conducting member. The second opening has a first open portion with an inner dimension to receive a first fastener and a second open portion with an inner dimension different than the first open portion. The second open portion is configured to receive a second fastener having an outer dimension different than the first fastener. The second open portion can have a substantially circular first and second open portions that overlap along the outer edges. An electrical assembly includes the electrical terminal and an electrically conducting base, and either a first fastener having a first dimension or a second fastener having a second dimension, where the dimension of the fasteners corresponding to dimension of a threaded hole in the base.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a transistor having a metal gate and a dielectric cap on top of the metal gate; and a source/drain contact directly on top of a source/drain region of the transistor, where the source/drain contact has a top portion of a first width in a length direction of the metal gate and a bottom portion of a second width in the length direction of the metal gate with the first width being narrower than the second width. A method of forming the same is also provided.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first field-effect transistor (FET) having a first source/drain region is formed. A second FET having a second source/drain region is formed, where the second FET is stacked above the first FET. A trench extending from above the second source/drain region to beneath the first source/drain region is formed, where the trench passes through portions of (i) the first source/drain region and (ii) the second source/drain region. A bottom contact is formed in the trench. A dielectric layer is formed in the trench, the dielectric layer on a top surface of the bottom contact. A top contact is formed in the trench, the top contact on a top surface of the dielectric layer.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for non-shared metal gate integrations for transistors. In a non-limiting embodiment of the invention, a first nanosheet stack is formed in a first region of a substrate and a second nanosheet stack is formed in a second region of the substrate. A first work function metal stack is formed around nanosheets in the first nanosheet stack and nanosheets in the second nanosheet stack, and a first sacrificial material is formed around the first work function metal stack. The first sacrificial material in the second nanosheet stack is replaced with a second sacrificial material and the first sacrificial material and the first work function metal stack in the first nanosheet stack are replaced with a second work function metal stack. The second sacrificial material in the second nanosheet stack is replaced with a third work function metal stack.

Abstract: A microelectronic device including a first nanosheet transistors adjacent to a second nanosheet transistor. The first nanosheet transistor includes a plurality of first nanosheets, and the second nanosheet transistor includes a plurality of second nanosheets. A source/drain located between the first nanosheet transistor and second nanosheet transistor. A first gate wraps around the plurality of first nanosheets. A second gate wraps around the plurality of second nanosheets. A first upper spacer located adjacent to the first gate, where the first upper spacer is in contact with at least three sides of the first gate. A second upper spacer located adjacent to the second gate, where the second upper spacer is in contact with at least three sides of the second gate. A backside interconnect connected to the source/drain, where the backside interconnect is in contact with the first upper spacer and the second upper spacer.

Abstract: A surface well fracturing system having fluid conduits connected to surface fracturing equipment with quick connect systems is provided. In one embodiment, a fracturing system includes a frac pump, a frac supply manifold, and a fracturing fluid conduit connected to route fracturing fluid between the frac pump and the frac supply manifold. The fracturing fluid conduit is connected to the frac pump or to the frac supply manifold by a quick connect apparatus, which includes a segmented clamp having multiple clamp segments mounted on a shared support. Additional systems, devices, and methods are also disclosed.

Abstract: A gimballed cantilevered actuating beam for sealing micro-valves is disclosed. The micro-valve includes an orifice plate and an orifice extending through the orifice plate. An actuating beam is disposed in spaced relation to the orifice plate. The actuating beam comprises a base portion separated from the orifice plate by a predetermined distance and a cantilevered portion extending from the base portion towards the orifice. An overlapping portion of the actuating beam overlaps the orifice and is flexibly affixed to the remainder of the cantilevered portion by at least one rib, allowing the overlapping portion to gimbal. A sealing structure is disposed at the overlapping portion, which seals the orifice when the actuating beam is in the closed position.

Abstract: The disclosure relates to chemokine CXCR4 receptor modulators and uses related thereto. The receptor modulators can be formulated to form pharmaceutical compositions comprising the disclosed compounds or pharmaceutically acceptable salts or prodrugs thereof. The compositions may be used for managing CXCR4 related conditions, typically prevention or treatment of viral infections abnormal cellular proliferation, retinal degeneration, inflammatory diseases, or as an immunostimulant or immunosuppressant or for managing cancer and may be administered with another active ingredient such as an antiviral agent or chemotherapeutic agent.

Abstract: Interconnect structures including signal lines, power lines and ground lines are configured for improvements in routing and scaling. Vertical stacking of the relatively wide power and ground lines allows for additional signal tracks in the same footprint of a standard cell or other electronic device. Alternatively, vertical stacking of the signal lines allows an increased number of signal tracks. Such interconnect structures are formed during back-end-of-line processing using subtractive or damascene interconnect integration techniques.

Abstract: A semiconductor device includes a back end of the line region on a frontside of the semiconductor device. A backside interconnect metallization layer is on a backside of the semiconductor device. A thermal conductivity channel is disposed between the back end of the line region and the backside interconnect metallization layer. The thermal conductivity channel includes a frontside super via and a backside super via connected by a contact therebetween.

Abstract: A blender system that includes a base that is selectively and operatively engaged with a container that is shown and described herein. The base may include a near field communications chip that may communicate with a near field communications chip of a container. The base also includes a motor that is selectively and operatively engaged with a blade disposed within a container.

Abstract: An inkjet ink that includes (A) metal nanoparticles (e.g., silver nanoparticles); (B) trimethylene glycol; and (C) 1,2-hexanediol; the inkjet ink being characterized by extended decap times, long running stability, quick drying properties, and the ability to form metallic printed images with high metallic luster (high gloss). Also provided are a printed article which includes a metallic film formed from the inkjet ink disposed on a substrate, and a method of forming a metallic printed image, whereby the inkjet ink is applied via a thermal inkjet printhead and is subsequently dried, such as with a near infrared heater.

Abstract: Systems and methods for reducing the amount of messages transmitted in large-scale distributed mesh networks are disclosed. Network components include transceivers and memory storing instructions which, when executed by a processing unit, reduce transmissions made by the transceiver within the network. The instructions executed by processing unit could (1) create an expiration parameter to limit the number of times a signal is retransmitted, (2) form groups of network components from which one or a few of the group network components are designated to respond on behalf of the group, (3) keep advertising transmissions dormant by default until called upon, (4) employ a time delay parameter for a time interval in which no transmission may be made, and (5) include message IDs in control signals that are transmitted.

Abstract: Semiconductor devices and methods of forming the same include a first transistor in a first region having a first work function metal layer. A second transistor in a second region has a second work function metal layer that overlaps a portion of the first work function metal layer and that has a vertical part above the portion of the first work function metal layer.