Abstract: A battery-operated palm stapler, an insert for holding a fastener, and a method of installing a fastener using the palm stapler. The stapler includes a housing with a telescoping barrel extending outwardly therefrom. An insert is engaged in the barrel’s bore and is held in place by magnets. The insert body defines a slot for receiving fasteners therein. The slot extends from a top wall of the body to a bottom wall thereof. At least one magnet is provided in the body adjacent the slot and is used to hold fasteners in a correct orientation for installation. A sensor probe provided in the body is operable to detect if voltage is carried in electrical cables adjacent which fasteners are to be installed. The probe deactivates a hammer actuating mechanism if voltage is detected. Inserts holding different types of fastener may be selectively engaged with the palm stapler.

Abstract: A system including a valve. The valve includes a valve body having an interior volume and a bore along a first axis. A stem extends along a second axis and a flow control element couples to the stem. The stem selectively moves the flow control element through the interior volume between a closed position and an open position relative to the bore. A valve insert system retains a pressurized lubricant in the interior volume.

Abstract: A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.

Abstract: A semiconductor device including a first nanodevice is located on a substrate, where the first nanodevice includes at least one channel. A first source/drain connected to the first nanodevice. A second nanodevice located on the substrate, where the second nanodevice includes at least one channel and a second source/drain connected to the second nanodevice. A first contact located above the first source/drain. A second contact located above the second source/drain. A contact cap located on top of the first contact and the second contact, where the contact cap has a first leg that extends downwards between the first contact and the second contact. The first leg of the contact cap is in contact with a first sidewall of the first contact, and a first sidewall of the second contact.

Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

Abstract: A planar filament 11f can include multiple materials to increase electron emission in desired directions and to suppress electron emission in undesired directions. The filament 11f can include a core-material CM between a top-material TM and a bottom-material BM. The top-material TM can have a lowest work function WFt; the bottom-material BM can have a highest work function WFb; and the core-material CM can have an intermediate work function WFc(WFt<WFc<WFb). A width Wt of the filament 11f at a top-side 31t can be greater than its width Wb at a bottom-side 31b (Wt>Wb). This shape makes it easier to coat the edges 31e with the bottom-material BM, because the edges 31e tilt toward and partially face the sputter target. This shape also helps direct more electrons to a center of the target 14, and reduce electron emission in undesired directions.

Abstract: Apparatus and associated methods relate to generating energy blocks on a blockchain corresponding to generation, transmission, and consumption of predetermined quanta of energy represented by corresponding records in an associated Merkle trie. In an illustrative example, individual energy data records may be hashed. Each hash may be stored in a leaf node of a Merkle trie. The individual energy data records may be aggregated to correspond to represent a predetermined quantum of energy. The individual energy data records may include energy generation records. The energy blocks may be associated with scheduling, delivery, and consumption data for the energy quantum. Various embodiments may advantageously provide secure, verifiable, and immutable tracking and processing of energy generation, transmission, and consumption of physical energy quanta across one or more distributed energy networks.

Abstract: Apparatus and associated methods relate to automatically load matching, in time, energy physically generated and transmitted to a consumption location across at least one tracking and processing infrastructure. In an illustrative example, a load pool (LP) may be created based on energy consumed at a physical location at one or more selected time periods. A generation pool (GP) may, for example, be created based on energy generated and physically available for consumption at the physical location during the time periods. Associations may be created, for example, between measurements in the GP of energy generated and transmitted and measurements in the LP of energy consumed. The associations may be created as a function of predetermined privileges associated with the consumption location and generation locations and/or physical transmission links corresponding to the GP during the time periods. Various embodiments may advantageously determine environmental impact based on location and time-based load matching.

Abstract: Interconnect structures including signal lines, power lines and ground lines are configured for improvements in routing and scaling. Vertical stacking of the relatively wide power and ground lines allows for additional signal tracks in the same footprint of a standard cell or other electronic device. Alternatively, vertical stacking of the signal lines allows an increased number of signal tracks. Such interconnect structures are formed during back-end-of-line processing using subtractive or damascene interconnect integration techniques.

Abstract: An apparatus including a substrate and a first nanosheet device located on the substrate. A second nanosheet device is located on the substrate, where the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device and the at least one first gate has a first width. At least one second gate located on the second nanosheet device and the at least one second gate has a second width. The first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device. The diffusion break prevents the first nanosheet device from contacting the second nanosheet device, and the diffusion break has a third width. The third width is larger than the first width and the second width.

Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

Abstract: Embodiments disclosed herein include a semiconductor structure having a first lower device and a second lower device laterally adjacent to the first lower device at a lower level of the semiconductor structure, a first upper device and a second upper device laterally adjacent to the first upper device at an upper level of the semiconductor structure. The upper level may be vertically above the lower level. The semiconductor structure may also include an angled via electrically connecting the lower device and the first upper device. The angled via may include an angled surface laterally between the first upper device and the second upper device that is angled toward the first upper device relative to a vertical axis.

Abstract: A semiconductor device having a self-aligned contact gate dielectric cap, or “SAC cap” over the gate stack and spacer. A SAC cap ear exists over the sidewall of a top portion of the spacer at a location where no S/D contact is formed. A method of forming the semiconductor device comprises: (i) forming gate stack; (ii) recessing ILD to create topography of the gate stack; (iii) forming selective gate cap deposition over the gate stack; and/or (iv) forming self-aligned contact with respect to the selective gate cap.

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate elevator analytics and/or elevator optimization components are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a prediction component that can predict a current destination of an elevator passenger based on historical elevator usage data of the elevator passenger. The computer executable components can further comprise an assignment component that can assign the elevator passenger to an elevator based on the current destination.

Abstract: A gate-all-around device includes a plurality of channel layers vertically stacked over a substrate, an inner spacer located between each of the plurality of channel layers, source/drain regions in contact with opposite ends of a first portion of the plurality of channel layers, and a first dielectric layer on opposite ends of a second portion of the plurality of channel layers located in a spacer region that is adjacent to the source/drain regions. A width of the first dielectric layer and the second portion of the plurality of channel layers is equal to a width of the inner spacer located between each of the plurality of channel layers.

Abstract: A handheld laser-based vehicle speed measurement device incorporating on-board data storage with GPS, compass, excess panning detection, and voice recognition technology, as well as, recording minimum and maximum speeds of a plurality of vehicles along a roadway and calculating the 85th percentile speed.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.

Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first, via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.

Abstract: A semiconductor structure is provided in which a via to buried power rail (VBPR) contact structure is present that has a via portion contacting a buried power rail and a non-via portion contacting a source/drain region of a first functional gate structure present in a first device region. A dielectric spacer structure including a base dielectric spacer and a replacement dielectric spacer is located between the VPBR contact structure and the first functional gate structure. The replacement dielectric spacer is composed of a gate cut trench dielectric material that is also present in a gate cut trench that is located between the first functional gate structure present in the first device region, and a second functional gate structure that is present in a second device region. The replacement dielectric spacer replaces a damaged region of a dielectric spacer that is originally present during VBPR formation.

Abstract: The disclosure relates to chemokine CXCR4 receptor modulators and uses related thereto. The receptor modulators can be formulated to form pharmaceutical compositions comprising the disclosed compounds or pharmaceutically acceptable salts or prodrugs thereof. The compositions may be used for managing CXCR4 related conditions, typically prevention or treatment of viral infections abnormal cellular proliferation, retinal degeneration, inflammatory diseases, or as an immunostimulant or immunosuppressant or for managing cancer and may be administered with another active ingredient such as an antiviral agent or chemotherapeutic agent.