Patents by Inventor Eric Neyret
Eric Neyret has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150221545Abstract: A method for producing a high quality useful layer of semiconductor material on a substrate. The method includes implanting at least two different atomic species into a face of a donor substrate to a controlled mean implantation depth to form a weakened zone therein and to define a useful layer. The implanting step is conducted to minimize low-frequency roughness at the weakened zone. Next, the method includes bonding a support substrate to the face of the donor substrate, and detaching the useful layer from the donor substrate along the weakened zone. A structure is thus formed that includes the useful layer on the support substrate with the useful layer presenting a surface for further processing. The technique also includes thermally treating the structure to minimize high-frequency roughness of the surface of the useful layer. The result is a surface having sufficient smoothness so that chemical-mechanical polishing (CMP) is not needed.Type: ApplicationFiled: February 18, 2015Publication date: August 6, 2015Inventors: Christophe Maleville, Eric Neyret, Nadia Ben Mohamed
-
Patent number: 8679944Abstract: The invention provides a method of trimming a structure that includes a first wafer bonded to a second wafer, with the first wafer having a chamfered edge. The method includes a first trimming step carried out over a first depth that includes at least the thickness of the first wafer and over a first width determined from the edge of the first wafer. A second trimming step is then carried out over a second depth that includes at least the thickness of the first wafer and over a second width that is less than the first width.Type: GrantFiled: July 31, 2009Date of Patent: March 25, 2014Assignee: SoitecInventors: Marcel Broekaart, Marion Migette, Sébastien Molinari, Eric Neyret
-
Patent number: 8461018Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.Type: GrantFiled: June 6, 2011Date of Patent: June 11, 2013Assignee: S.O.I.TEC Silicon on Insulator TechnologiesInventors: Eric Neyret, Sebastien Kerdiles
-
Patent number: 8389412Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.Type: GrantFiled: March 17, 2010Date of Patent: March 5, 2013Assignee: SoitecInventors: Walter Schwarzenbach, Sébastien Kerdiles, Patrick Reynaud, Ludovic Ecarnot, Eric Neyret
-
Patent number: 8273636Abstract: Methods for forming semiconductor structures comprising a layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect to defects and resulting structures therefrom. For example, a semiconductor-on-insulator (SeOI) structure can be formed by a method comprising:—providing a donor substrate having a first density of vacancy clusters;—providing an insulating layer; —transferring a thin layer from the donor substrate to a support substrate with the insulating layer thereon;—curing the transferred thin layer to reduce the first density of vacancy clusters to a second density; and being characterized in that the step of providing an insulating layer comprises providing an oxygen barrier layer to be in contact with the transferred thin layer, the oxygen barrier layer limiting diffusion of oxygen toward the thin layer during the curing.Type: GrantFiled: October 27, 2006Date of Patent: September 25, 2012Assignee: SoitecInventors: Eric Neyret, Oleg Kononchuk
-
Patent number: 8216916Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.Type: GrantFiled: April 19, 2007Date of Patent: July 10, 2012Assignee: S.O.I. TEC Silicon on Insulator TechnologiesInventors: Eric Neyret, Sebastien Kerdiles
-
Publication number: 20120021613Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.Type: ApplicationFiled: March 17, 2010Publication date: January 26, 2012Inventors: Walter Schwarzenbach, Sébastien Kerdiles, Patrick Reynaud, Ludovic Ecarnot, Eric Neyret
-
Publication number: 20110233720Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.Type: ApplicationFiled: June 6, 2011Publication date: September 29, 2011Applicant: S.O.I.TEC Silicon on Insulator TechnologiesInventors: Eric Neyret, Sebastien Kerdiles
-
Patent number: 7947571Abstract: The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cm2 the implanting is carried out with a dose of less than 2.3×106 atoms per cm2 and the thinning is an oxidation step conducted at a temperature of less than 925° C.Type: GrantFiled: June 4, 2009Date of Patent: May 24, 2011Assignee: S.O.I. Tec Silicon on Insulator TechnologiesInventors: Luciana Capello, Oleg Kononchuk, Eric Neyret, Alexandra Abbadie, Walter Schwarzenbach
-
Publication number: 20110117691Abstract: The invention relates to a method of trimming a structure that includes a first wafer bonded to a second wafer, with the first wafer having a chamfered edge. The method includes a first step of trimming the edge of the first wafer by mechanical machining over a predetermined depth in the first wafer. This first trimming step is followed by a second step of non-mechanical trimming over at least the remaining thickness of the first wafer.Type: ApplicationFiled: July 31, 2009Publication date: May 19, 2011Inventors: Marcel Broekaart, Marion Migette, Sébastien Molinari, Eric Neyret
-
Patent number: 7939427Abstract: A process for fabricating a silicon on insulator (SOI) substrate by co-implanting atomic or ionic species into a semiconductor donor substrate to form a weakened zone therein, the weakened zone forming a boundary between a thin silicon active layer and the remainder of the donor substrate. The donor substrate is then bonded to a semiconductor receiver substrate by molecular adhesion, resulting in a layer of buried silicon interposed between the donor substrate and the receiver substrate. The remainder of the donor substrate is detached along the weakened zone to obtain a SOI substrate with the receiver substrate covered with the buried oxide layer and the thin silicon active layer. The silicon active layer is then thermally annealed for at least 10 minutes in a gaseous atmosphere containing hydrogen, argon or both at a temperature of at least 950° C. but not exceeding 1100° C.Type: GrantFiled: September 4, 2007Date of Patent: May 10, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Eric Neyret, François Boedt
-
Publication number: 20110097871Abstract: Methods for forming semiconductor structures comprising a layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect of defects, and resulting structures therefrom. For example, a semiconductor on insulator (SeOI) structure can be formed by a method comprising: —providing a donor substrate (1) having a first density of vacancy clusters; —providing an insulating layer (3); —transferring a thin layer (10) from the donor substrate (1) to a support substrate (2) with the insulating layer (3) thereon; —curing the transferred thin layer (10) to reduce the first density of vacancy clusters to a second density; and being characterized in that the step of providing an insulating layer (30) comprises providing an oxygen barrier layer (4) to be in contact with the transferred thin layer (10), said oxygen barrier layer limiting diffusion of oxygen towards the thin layer during the curing.Type: ApplicationFiled: October 27, 2006Publication date: April 28, 2011Inventors: Eric Neyret, Oleg Kononchuk
-
Publication number: 20110097874Abstract: The invention provides a method of trimming a structure that includes a first wafer bonded to a second wafer, with the first wafer having a chamfered edge. The method includes a first trimming step carried out over a first depth that includes at least the thickness of the first wafer and over a first width determined from the edge of the first wafer. A second trimming step is then carried out over a second depth that includes at least the thickness of the first wafer and over a second width that is less than the first width.Type: ApplicationFiled: July 31, 2009Publication date: April 28, 2011Inventors: Marcel Broekaart, Marion Migette, Sebastian Molinari, Eric Neyret
-
Patent number: 7883628Abstract: A method for reducing the roughness of a free surface of a semiconductor wafer that includes establishing a first atmosphere in an annealing chamber, replacing the first atmosphere with a second atmosphere that includes a gas selected to and in an amount to substantially eliminate or reduce pollutants on a wafer, and exposing the free surface of the wafer to the second atmosphere to substantially eliminate or reduce pollutants thereon. The second atmosphere is then replaced with a third atmosphere that includes pure, and rapid thermal annealing is performed on the wafer exposed to the third atmosphere in the annealing chamber to substantially reduce the roughness of the free surface of the wafer.Type: GrantFiled: July 27, 2005Date of Patent: February 8, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Eric Neyret, Ludovic Ecarnot, Emmanuel Arene
-
Patent number: 7863158Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.Type: GrantFiled: May 29, 2007Date of Patent: January 4, 2011Assignee: S.O.I.TEC Silicon on Insulator TechnologiesInventors: Eric Neyret, Sebastien Kerdiles
-
Patent number: 7749910Abstract: The invention provides a method for reducing the roughness of a free surface of a semiconductor wafer that includes removing material from the free surface of the wafer to provide a treated wafer, and performing a first rapid thermal annealing on the treated wafer in a pure argon atmosphere to substantially reduce the roughness of the free surface of the treated wafer. The material removal is selected and conducted to improve the effectiveness of the subsequent rapid thermal annealing in reducing the roughness of the free surface of the treated wafer.Type: GrantFiled: July 27, 2005Date of Patent: July 6, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Eric Neyret, Ludovic Ecarnot, Christophe Maleville
-
Publication number: 20100052092Abstract: The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cm2 the implanting is carried out with a dose of less than 2.3×106 atoms per cm2 and the thinning is an oxidation step conducted at a temperature of less than 925° C.Type: ApplicationFiled: June 4, 2009Publication date: March 4, 2010Inventors: Luciana Capello, Oleg Kononchuk, Eric Neyret, Alexandra Abbadie, Walter Schwarzenbach
-
Patent number: 7666758Abstract: A process for fabricating a silicon on insulator (SOI) substrate by forming a weakened zone within a semiconductor donor substrate to define a thick layer having a thickness of greater 150 nm and form a boundary between the thick layer and a remainder of the donor substrate, bonding the donor substrate to a semiconductor receiver substrate, with one of the substrates including an oxide layer that is present between the donor and receiver substrates after bonding; detaching a remainder of the donor substrate along the weakened zone to obtain a semifinished SOI substrate comprising the receiver substrate, the oxide layer and the thick layer; and finishing the semifinished SOI substrate by thinning the thick layer to obtain a silicon layer having a thickness is less than that of the thick layer but greater than 150 nm; long annealing the semifinished SOI substrate in a gaseous atmosphere comprising hydrogen and/or argon; and thinning the thin layer to obtain an ultrathin layer with a thickness of 150 nm or lessType: GrantFiled: August 31, 2007Date of Patent: February 23, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Eric Neyret
-
Patent number: 7514341Abstract: The invention relates to a process for the formation of a structure comprising a thin layer made of semiconductor material on a substrate, including the steps of providing a zone of weakness in a donor substrate; bonding the donor substrate to a support substrate; detaching a portion of the donor substrate to transfer it to the support substrate, wherein the detaching includes applying heat treating the donor substrate to weaken the zone of weakness without initiating detachment and applying an energy pulse to provoke self-maintained detachment of the donor substrate portion to transfer it to the support substrate; and subjecting the transferred portion of the donor substrate to a finishing operation to form a thin layer.Type: GrantFiled: February 16, 2006Date of Patent: April 7, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Eric Neyret, Alice Boussagol, Nadia Ben Mohamed
-
Publication number: 20090035920Abstract: A process for fabricating a silicon on insulator (SOI) substrate by co-implanting atomic or ionic species into a semiconductor donor substrate to form a weakened zone therein, the weakened zone forming a boundary between a thin silicon active layer and the remainder of the donor substrate. The donor substrate is then bonded to a semiconductor receiver substrate by molecular adhesion, resulting in a layer of buried silicon interposed between the donor substrate and the receiver substrate. The remainder of the donor substrate is detached along the weakened zone to obtain a SOI substrate with the receiver substrate covered with the buried oxide layer and the thin silicon active layer. The silicon active layer is then thermally annealed for at least 10 minutes in a gaseous atmosphere containing hydrogen, argon or both at a temperature of at least 950° C. but not exceeding 1100° C.Type: ApplicationFiled: September 4, 2007Publication date: February 5, 2009Inventors: Eric NEYRET, Francois Boedt