Patents by Inventor Eric Neyret

Eric Neyret has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050230754
    Abstract: A preventive treatment method for a multilayer semiconductor wafer is described. The semiconductor wafer includes a supporting substrate, at least one intermediate layer and a surface layer in which an intermediate layer has an exposed lateral edge and the wafer is to be subjected to a subsequent treatment. The method includes encapsulating the exposed lateral edge of the intermediate layer with a portion of the surface layer to prevent attack on the peripheral edge during the subsequent treatment.
    Type: Application
    Filed: June 22, 2005
    Publication date: October 20, 2005
    Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A., a French corporate
    Inventors: Eric Neyret, Christophe Maleville
  • Publication number: 20050202658
    Abstract: A method for limiting slip lines in a semiconductor substrate including a support layer and a useful semiconductor layer that is transferred to the support layer. The method includes precipitating at least a portion of interstitial oxygen in the support layer by a series of heat treatments conducted after bonding of the useful semiconductor layer to the support layer. The heat treatments occur at a temperature and a time sufficient to reduce the generation of slip lines therein.
    Type: Application
    Filed: May 5, 2004
    Publication date: September 15, 2005
    Inventor: Eric Neyret
  • Patent number: 6939783
    Abstract: A preventive treatment method for a multilayer semiconductor wafer is described. The semiconductor wafer includes a supporting substrate, at least one intermediate layer and a surface layer in which an intermediate layer has an exposed lateral edge and the wafer is to be subjected to a subsequent treatment. The method includes encapsulating the exposed lateral edge of the intermediate layer with a portion of the surface layer to prevent attack on the peripheral edge during the subsequent treatment.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: September 6, 2005
    Assignee: S.O.I.Tec Silicon on Insulator Technologies, S.A.
    Inventors: Eric Neyret, Christophe Maleville
  • Patent number: 6903032
    Abstract: A method for preparing a semiconductor wafer wherein rapid thermal annealing is conducted to smooth a free surface of a superficial zone that is supported by the wafer. The improvement includes treating the superficial zone before conducting the rapid thermal annealing to prevent pitting in the superficial zone during the rapid thermal annealing.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: June 7, 2005
    Assignee: S.O.I.TEC Silicon on Insulator Technologies S.A.
    Inventors: Christophe Maleville, Eric Neyret
  • Publication number: 20050094990
    Abstract: A method for heat treating a multilayer semiconductor wafer having a central region and a peripheral edge each having a surface. The method includes selecting thickness values for the layers of the wafer to provide substantially equivalent heat absorption coefficients both in the central region and the edge of the wafer. This results in a substantially equivalent temperature being attained over the surface of the central region and the peripheral edge during thermal treatment. In turn, that prevents the appearance of slip lines on those surfaces while also preventing deformation of the wafer due to the thermal treatment. To achieve the desired thickness, layers or portions of layers can be selectively added or otherwise provided upon the central region or peripheral edge of the wafer, or on both, to modify the heat absorption coefficient of the wafer.
    Type: Application
    Filed: December 13, 2004
    Publication date: May 5, 2005
    Applicant: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A., a French corporate
    Inventors: Eric Neyret, Christophe Maleville
  • Patent number: 6853802
    Abstract: A method for heat treating a multilayer semiconductor wafer having a central region and a peripheral edge each having a surface. The method includes thermally treating selected portions of the peripheral edge to compensate for local differences in heat absorption. This establishes a substantially equivalent temperature over both the surface of the central region and the surface of the peripheral edge to prevent the appearance of slip lines on those surfaces.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: February 8, 2005
    Assignee: S.O.I. Tec Silicon on Insulator Technologies S.A.
    Inventors: Eric Neyret, Christophe Maleville
  • Publication number: 20050026426
    Abstract: A method for producing a high quality useful layer of semiconductor material on a substrate. The method includes implanting at least two different atomic species into a face of a donor substrate to a controlled mean implantation depth to form a weakened zone therein and to define a useful layer. The implanting step is conducted to minimize low-frequency roughness at the weakened zone. Next, the method includes bonding a support substrate to the face of the donor substrate, and detaching the useful layer from the donor substrate along the weakened zone. A structure is thus formed that includes the useful layer on the support substrate with the useful layer presenting a surface for further processing. The technique also includes thermally treating the structure to minimize high-frequency roughness of the surface of the useful layer. The result is a surface having sufficient smoothness so that chemical mechanical polishing (CMP) is not needed.
    Type: Application
    Filed: October 21, 2003
    Publication date: February 3, 2005
    Inventors: Christophe Maleville, Eric Neyret, Nadia Ben Mohamed
  • Publication number: 20040197963
    Abstract: A preventive treatment method for a multilayer semiconductor wafer is described. The semiconductor wafer includes a supporting substrate, at least one intermediate layer and a surface layer in which an intermediate layer has an exposed lateral edge and the wafer is to be subjected to a subsequent treatment. The method includes encapsulating the exposed lateral edge of the intermediate layer with a portion of the surface layer to prevent attack on the peripheral edge during the subsequent treatment.
    Type: Application
    Filed: February 20, 2004
    Publication date: October 7, 2004
    Inventors: Eric Neyret, Christophe Maleville
  • Publication number: 20040171257
    Abstract: The invention provides a method of reducing the roughness of the free surface of a wafer of semiconductor material by applying a rapid thermal annealing process under a pure argon atmosphere for a time sufficient to uniformly heat and smooth the free surface of the wafer.
    Type: Application
    Filed: December 30, 2003
    Publication date: September 2, 2004
    Inventors: Eric Neyret, Ludovic Ecarnot
  • Publication number: 20040161948
    Abstract: A method for preparing a semiconductor wafer wherein rapid thermal annealing is conducted to smooth a free surface of a superficial zone that is supported by the wafer. The improvement includes treating the superficial zone before conducting the rapid thermal annealing to prevent pitting in the superficial zone during the rapid thermal annealing.
    Type: Application
    Filed: January 8, 2004
    Publication date: August 19, 2004
    Inventors: Christophe Maleville, Eric Neyret
  • Publication number: 20040151483
    Abstract: A method for heat treating a multilayer semiconductor wafer having a central region and a peripheral edge each having a surface. The method includes thermally treating selected portions of the peripheral edge to compensate for local differences in heat absorption. This establishes a substantially equivalent temperature over both the surface of the central region and the surface of the peripheral edge to prevent the appearance of slip lines on those surfaces.
    Type: Application
    Filed: November 3, 2003
    Publication date: August 5, 2004
    Inventors: Eric Neyret, Christophe Maleville
  • Publication number: 20040106303
    Abstract: A method for minimizing slip line faults on a surface of a semiconductor wafer that has been obtained using a transfer technique. The method includes heating the semiconductor wafer from an ambient temperature to a first higher temperature and pausing the heating at the first higher temperature for a time sufficient to stabilize the wafer. Then the wafer is heated further from the first higher temperature to a target higher temperature during a predetermined time interval. The further heating during an initial portion of the time interval is conducted at a relatively low heating rate and the heating during a final portion of the time interval is conducted at a relatively higher heating rate to thus minimize slip line faults in the surface of the wafer.
    Type: Application
    Filed: September 25, 2003
    Publication date: June 3, 2004
    Inventors: Eric Neyret, Christophe Maleville, Ludovic Ecarnot