Patents by Inventor Eric Neyret

Eric Neyret has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7485545
    Abstract: A method for configuring a process for treating a semiconductor wafer. A minimum layer thickness of a transferred layer to be provided is determined to obtain a processed layer that has a preselected target thickness and target maximum density of through holes that extend completely therethrough, by conducting a predetermined finishing sequence of operations that improve the surface quality of the layer. The minimum thickness is determined such that the density of through holes remains below the target maximum density after each operation in the finishing sequence.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: February 3, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Nadia Ben Mohamed, Eric Neyret, Daniel Delprat
  • Publication number: 20080188060
    Abstract: A process for fabricating a silicon on insulator (SOI) substrate by forming a weakened zone within a semiconductor donor substrate to define a thick layer having a thickness of greater 150 nm and form a boundary between the thick layer and a remainder of the donor substrate, bonding the donor substrate to a semiconductor receiver substrate, with one of the substrates including an oxide layer that is present between the donor and receiver substrates after bonding; detaching a remainder of the donor substrate along the weakened zone to obtain a semifinished SOI substrate comprising the receiver substrate, the oxide layer and the thick layer; and finishing the semifinished SOI substrate by thinning the thick layer to obtain a silicon layer having a thickness is less than that of the thick layer but greater than 150 nm; long annealing the semifinished SOI substrate in a gaseous atmosphere comprising hydrogen and/or argon; and thinning the thin layer to obtain an ultrathin layer with a thickness of 150 nm or less
    Type: Application
    Filed: August 31, 2007
    Publication date: August 7, 2008
    Inventor: Eric NEYRET
  • Patent number: 7405136
    Abstract: This invention provides methods for manufacturing compound-material wafers and methods for recycling donor substrates that results from manufacturing compound-material wafers. The provided methods includes at least one further thermal treatment step configured to at least partially reduce oxygen precipitates and/or nuclei. Reduction of oxygen precipitates and/or nuclei, improves the recycling rate of the donor substrate.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: July 29, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Daniel Delprat, Eric Neyret, Oleg Kononchuk, Patrick Reynaud, Michael Stinco
  • Publication number: 20080014713
    Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.
    Type: Application
    Filed: April 19, 2007
    Publication date: January 17, 2008
    Inventors: Eric Neyret, Sebastien Kerdiles
  • Publication number: 20080014718
    Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.
    Type: Application
    Filed: May 29, 2007
    Publication date: January 17, 2008
    Applicant: S.O.I TEC Silicon on Insulator Technologies S.A.
    Inventors: Eric Neyret, Sebastien Kerdiles
  • Publication number: 20070298606
    Abstract: A method for manufacturing a semiconductor multilayer wafer by manufacturing an intermediate multilayer wafer having a polished layer from which a surface layer is obtained. The surface roughness is reduced by chemical-mechanical polishing (CMP) removal of part of the polish layer with the CMP monitored through reflectometry of light. The reflectometry produces a response that includes reference points associated with a known thickness of the polish layer and the CMP is stopped once a predetermined reference point has been reached. The method includes conducting a preliminary calibration of the CMP to define a preliminary thickness which corresponds to a preliminary value of thickness of the polish layer, wherein the preliminary thickness is defined by the total of a thickness of polish layer known associated with the predetermined reference point, and a thickness to be removed, and a thickness for the polish layer is provided which is substantially equal to the preliminary thickness.
    Type: Application
    Filed: September 7, 2007
    Publication date: December 27, 2007
    Inventors: Eric Neyret, Cedric Angellier, Veronique Duquennoy-pont
  • Patent number: 7285471
    Abstract: Processes for forming semiconductor structure comprising a transfer layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect to defects and resulting structures therefrom. For example, a semiconductor on insulator (“SeOI”) structure can be formed using a donor substrate, a support substrate and an insulating layer. The donor substrate may be formed using CZ pulling of semiconductor material at a rate that results in the existence of vacancy clusters. An insulating layer for the SeOI structure can be formed by depositing an oxide layer on the donor or support substrate. An insulating layer can also be formed by thermal oxidizing the support substrate. An SeOI structure can be formed by combining the donor substrate, the support substrate, and the insulating layer there between, and detaching the combination including a thin layer of the donor substrate using a zone of weakness that was formed in the donor substrate.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: October 23, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Christophe Maleville, Eric Neyret
  • Publication number: 20070216042
    Abstract: This invention provides methods for manufacturing compound-material wafers and methods for recycling donor substrates that results from manufacturing compound-material wafers. The provided methods includes at least one further thermal treatment step configured to at least partially reduce oxygen precipitates and/or nuclei. Reduction of oxygen precipitates and/or nuclei, improves the recycling rate of the donor substrate.
    Type: Application
    Filed: June 21, 2006
    Publication date: September 20, 2007
    Inventors: Daniel Delprat, Eric Neyret, Oleg Kononchuk, Patrick Reynaud, Michael Stinco
  • Publication number: 20070148910
    Abstract: The invention relates to a process for the formation of a structure comprising a thin layer made of semiconductor material on a substrate, including the steps of providing a zone of weakness in a donor substrate; bonding the donor substrate to a support substrate; detaching a portion of the donor substrate to transfer it to the support substrate, wherein the detaching includes applying heat treating the donor substrate to weaken the zone of weakness without initiating detachment and applying an energy pulse to provoke self-maintained detachment of the donor substrate portion to transfer it to the support substrate; and subjecting the transferred portion of the donor substrate to a finishing operation to form a thin layer.
    Type: Application
    Filed: February 16, 2006
    Publication date: June 28, 2007
    Inventors: Eric Neyret, Alice Boussagol, Nadia Ben Mohamed
  • Patent number: 7190029
    Abstract: A preventive treatment method for a multilayer semiconductor wafer is described. The semiconductor wafer includes a supporting substrate, at least one intermediate layer and a surface layer in which an intermediate layer has an exposed lateral edge and the wafer is to be subjected to a subsequent treatment. The method includes encapsulating the exposed lateral edge of the intermediate layer with a portion of the surface layer to prevent attack on the peripheral edge during the subsequent treatment.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: March 13, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Eric Neyret, Christophe Maleville
  • Patent number: 7138344
    Abstract: A method for minimizing slip line faults on a surface of a semiconductor wafer that has been obtained using a transfer technique. The method includes heating the semiconductor wafer from an ambient temperature to a first higher temperature and pausing the heating at the first higher temperature for a time sufficient to stabilize the wafer. Then the wafer is heated further from the first higher temperature to a target higher temperature during a predetermined time interval. The further heating during an initial portion of the time interval is conducted at a relatively low heating rate and the heating during a final portion of the time interval is conducted at a relatively higher heating rate to thus minimize slip line faults in the surface of the wafer.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: November 21, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Eric Neyret, Christophe Maleville, Ludovic Ecarnot
  • Publication number: 20060223283
    Abstract: A method for producing a high quality useful layer of semiconductor material on a substrate. The method includes implanting at least two different atomic species into a face of a donor substrate to a controlled mean implantation depth to form a weakened zone therein and to define a useful layer. The implanting step is conducted to minimize low-frequency roughness at the weakened zone. Next, the method includes bonding a support substrate to the face of the donor substrate, and detaching the useful layer from the donor substrate along the weakened zone. A structure is thus formed that includes the useful layer on the support substrate with the useful layer presenting a surface for further processing. The technique also includes thermally treating the structure to minimize high-frequency roughness of the surface of the useful layer. The result is a surface having sufficient smoothness so that chemical mechanical polishing (CMP) is not needed.
    Type: Application
    Filed: June 5, 2006
    Publication date: October 5, 2006
    Inventors: Christophe Maleville, Eric Neyret, Nadia Ben Mohamed
  • Publication number: 20060172508
    Abstract: Processes for forming semiconductor structure comprising a transfer layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect to defects and resulting structures therefrom. For example, a semiconductor on insulator (“SeOI”) structure can be formed using a donor substrate, a support substrate and an insulating layer. The donor substrate may be formed using CZ pulling of semiconductor material at a rate that results in the existence of vacancy clusters. An insulating layer for the SeOI structure can be formed by depositing an oxide layer on the donor or support substrate. An insulating layer can also be formed by thermal oxidizing the support substrate. An SeOI structure can be formed by combining the donor substrate, the support substrate, and the insulating layer there between, and detaching the combination including a thin layer of the donor substrate using a zone of weakness that was formed in the donor substrate.
    Type: Application
    Filed: May 13, 2005
    Publication date: August 3, 2006
    Inventors: Christophe Maleville, Eric Neyret
  • Patent number: 7081399
    Abstract: A method for producing a high quality useful layer of semiconductor material on a substrate. The method includes implanting at least two different atomic species into a face of a donor substrate to a controlled mean implantation depth to form a weakened zone therein and to define a useful layer. The implanting step is conducted to minimize low-frequency roughness at the weakened zone. Next, the method includes bonding a support substrate to the face of the donor substrate, and detaching the useful layer from the donor substrate along the weakened zone. A structure is thus formed that includes the useful layer on the support substrate with the useful layer presenting a surface for further processing. The technique also includes thermally treating the structure to minimize high-frequency roughness of the surface of the useful layer. The result is a surface having sufficient smoothness so that chemical mechanical polishing (CMP) is not needed.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: July 25, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Christophe Maleville, Eric Neyret, Nadia Ben Mohamed
  • Publication number: 20060141755
    Abstract: A method for configuring a process for treating a semiconductor wafer. A minimum layer thickness of a transferred layer to be provided is determined to obtain a processed layer that has a preselected target thickness and target maximum density of through holes that extend completely therethrough, by conducting a predetermined finishing sequence of operations that improve the surface quality of the layer. The minimum thickness is determined such that the density of through holes remains below the target maximum density after each operation in the finishing sequence.
    Type: Application
    Filed: January 10, 2006
    Publication date: June 29, 2006
    Inventors: Nadia Ben Mohamed, Eric Neyret, Daniel Delprat
  • Patent number: 7049250
    Abstract: A method for heat treating a multilayer semiconductor wafer having a central region and a peripheral edge each having a surface. The method includes selecting thickness values for the layers of the wafer to provide substantially equivalent heat absorption coefficients both in the central region and the edge of the wafer. This results in a substantially equivalent temperature being attained over the surface of the central region and the peripheral edge during thermal treatment. In turn, that prevents the appearance of slip lines on those surfaces while also preventing deformation of the wafer due to the thermal treatment. To achieve the desired thickness, layers or portions of layers can be selectively added or otherwise provided upon the central region or peripheral edge of the wafer, or on both, to modify the heat absorption coefficient of the wafer.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: May 23, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Eric Neyret, Christophe Maleville
  • Patent number: 7001832
    Abstract: A method for limiting slip lines in a semiconductor substrate including a support layer and a useful semiconductor layer that is transferred to the support layer. The method includes precipitating at least a portion of interstitial oxygen in the support layer by a series of heat treatments conducted after bonding of the useful semiconductor layer to the support layer. The heat treatments occur at a temperature and a time sufficient to reduce the generation of slip lines therein.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: February 21, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventor: Eric Neyret
  • Publication number: 20060035445
    Abstract: The invention provides a method for reducing the roughness of a free surface of a semiconductor wafer that includes removing material from the free surface of the wafer to provide a treated wafer, and performing a first rapid thermal annealing on the treated wafer in a pure argon atmosphere to substantially reduce the roughness of the free surface of the treated wafer. The material removal is selected and conducted to improve the effectiveness of the subsequent rapid thermal annealing in reducing the roughness of the free surface of the treated wafer.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 16, 2006
    Inventors: Eric Neyret, Ludovic Ecarnot, Christophe Maleville
  • Publication number: 20060024908
    Abstract: A method for reducing the roughness of a free surface of a semiconductor wafer that includes establishing a first atmosphere in an annealing chamber, replacing the first atmosphere with a second atmosphere that includes a gas selected to and in an amount to substantially eliminate or reduce pollutants on a wafer, and exposing the free surface of the wafer to the second atmosphere to substantially eliminate or reduce pollutants thereon. The second atmosphere is then replaced with a third atmosphere that includes pure, and rapid thermal annealing is performed on the wafer exposed to the third atmosphere in the annealing chamber to substantially reduce the roughness of the free surface of the wafer.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 2, 2006
    Inventors: Eric Neyret, Ludovic Ecarnot, Emmanuel Arene
  • Patent number: 6962858
    Abstract: The invention provides a method of reducing the roughness of the free surface of a wafer of semiconductor material by applying a rapid thermal annealing process under a pure argon atmosphere for a time sufficient to uniformly heat and smooth the free surface of the wafer.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: November 8, 2005
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Eric Neyret, Ludovic Ecarnot