Abstract: Quantum efficiency in an active pixel sensor improved by proper sizing and shaping of the contacts. The photodiode elements are formed of special shapes that are optimized for obtaining diffusion of charge, rather than obtaining the charge directly. Photogates are formed with a thinned polysilicon covering.

Abstract: A digital median filter is made using a successive approximation A/D converter circuit, which is arranged to produce an output based on majority weighting.

Abstract: A semiconductor imaging system preferably having an active pixel sensor array compatible with a CMOS fabrication process. Color-filtering elements such as polymer filters and wavelength-converting phosphors can be integrated with the image sensor.

Abstract: Wedge-shaped optical reflectors are used to reflect optical energy. Certain optical energy is incoming toward an area of the chip that is housing the non-photosensitive electronics. Wedges are used to reflect that radiation toward the photosensitive electronics.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. The imaging device can also include an electronic shutter formed on the substrate adjacent the photogate, and/or a storage section to allow for simultaneous integration.

Abstract: An image sensor operable to vary the output spatial resolution according to a received light level while maintaining a desired signal-to-noise ratio. Signals from neighboring pixels in a pixel patch with an adjustable size are added to increase both the image brightness and signal-to-noise ratio. One embodiment comprises a sensor array for receiving input signals, a frame memory array for temporarily storing a full frame, and an array of self-calibration column integrators for uniform column-parallel signal summation. The column integrators are capable of substantially canceling fixed pattern noise.

Abstract: A current-mode analog-to-digital converter based on a current copier circuit with a constant bias current that is independent of the input signals. A second-order incremental .SIGMA.-.DELTA. conversion configuration is implemented. An array of such analog-to-digital converters can be integrated onto the focal plane of an imaging sensor array to achieve column-wise parallel analog-to-digital conversion.

Abstract: An imaging pixel array with event detectors for detecting input light signals and activating the imaging pixel array based on a predetermined threshold intensity of an input light. Each event detector is preferably made of auxiliary photosensitive pixels with a thresholding circuit. The imaging pixel array is activated to perform signal integration if the input light signal is above the threshold intensity. A self-triggered X-ray sensor can be realized with such event detectors. A CMOS active pixel sensor can be used as the imaging pixel array with advantages.

Abstract: A capacitively-coupled successive approximation analog-to-digital converter utilizes a capacitively coupled multiplying digital to analog converter to generate a succession of voltages which are compared to the input voltage to be digitized. The capacitively coupled multiplying digital to analog converter generates the required succession of analog voltage levels utilizing very low power in response to digital signals. A double-sided version of the invention processes differential inputs with improved common-non-ideality mode rejection.

Abstract: Single substrate device is formed to have an image acquistition device and a controller. The controller on the substrate controls the system operation.

Abstract: An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes charge integrating amplifiers in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

Abstract: A solid-state focal-plane imaging system comprises an N.times.N array of high gain, low-noise unit cells, each unit cell being connected to a different one of photovoltaic detector diodes, one for each unit cell, interspersed in the array for ultralow level image detection and a plurality of digital counters coupled to the outputs of the unit cell by a multiplexer (either a separate counter for each unit cell or a row of N of counters time shared with N rows of digital counters). Each unit cell includes two self-biasing cascode amplifiers in cascade for a high charge-to-voltage conversion gain (>1 mV/e.sup.-) and an electronic switch to reset input capacitance to a reference potential in order to be able to discriminate detection of an incident photon by the photoelectron (e.sup.-) generated in the detector diode at the input of the first cascode amplifier in order to count incident photons individually in a digital counter connected to the output of the second cascode amplifier.

Abstract: The invention computes the optimum path across a terrain or topology represented by an array of parallel processor cells interconnected between neighboring cells by links extending along different directions to the neighboring cells. Such an array is preferably implemented as a high-speed integrated circuit. The computation of the optimum path is accomplished by, in each cell, receiving stimulus signals from neighboring cells along corresponding directions, determining and storing the identity of a direction along which the first stimulus signal is received, broadcasting a subsequent stimulus signal to the neighboring cells after a predetermined delay time, whereby stimulus signals propagate throughout the array from a starting one of the cells. After propagation of the stimulus signals throughout the array, a master processor traces back from a selected destination cell to the starting cell along an optimum path of the cells in accordance with the identity of the directions stored in each of the cells.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Abstract: A monolithic semiconductor imager includes an indium-based III-V compound semiconductor monolithic active layer of a first conductivity type, an array of plural focal plane cells on the active layer, each of the focal plane cells including a photogate over a top surface of the active layer, a readout circuit dedicated to the focal plane cell including plural transistors formed monolithically with the monolithic active layer and a single-stage charge coupled device formed monolithically with the active layer between the photogate and the readout circuit for transferring photo-generated charge accumulated beneath the photogate during an integration period to the readout circuit. The photogate includes thin epitaxial semiconductor layer of a second conductivity type overlying the active layer and an aperture electrode overlying a peripheral portion of the thin epitaxial semiconductor layer, the aperture electrode being connectable to a photogate bias voltage.

Abstract: A process for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface of the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Abstract: An electromagnetic jaw clutch has interengageable teeth with gaps between them to facilitate engaging the clutch when there is some relative rotation between these teeth. The teeth are defined on one hub and on the armature. The second hub is plastic and a spring pulls the armature toward this second hub to disengage the clutch. The spring may be integrally formed with the plastic second hub.

Abstract: A charge-coupled device (CCD) is formed by first defining relatively deep trenches having relatively small lateral dimensions in the surface of a silicon bulk region. A relatively thin silicon dioxide layer is formed over the silicon surface and inside each trench to cover the internal surfaces thereof. Finally, respective conducting electrode layers are formed over each trench covering the silicon dioxide layer within the trench. Such a CCD structure provides improved packing density and versatility of function over a conventional surface electrode CCD structures. When used in an image-sensing device, the trench-defined CCD structure provides improved quantum efficiency, owing to the deeper potential wells which may be formed in such structures for capturing photogenerated charge carriers.

Abstract: An electromagnetic motorbrake has three wear compensating studs with threaded portions that receive nuts. The threaded nuts define cylindrical wrap surfaces for spring clutch elements that are coupled between the armature and the pressure plate of the brake by a bellcrank to be sequentially wrapped to turn the nuts as required to automatically take up any excessive gap between the armature and the electromagnet due to wear of the friction disc between the armature and the pressure plate.

Abstract: Submicron structure fabrication is accomplished by providing vapor chemical erosion of a compound crystal by suppressing the more volatile elements so that the less volatile element is provided with an anti-agglomeration and erosion rate limiting capability which can be followed by subsequent regrowth in the same environment. The erosion is sensitive to crystallographic orientation.