Patents by Inventor Erich Griebl
Erich Griebl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160126149Abstract: According to various embodiments, a method for processing a substrate may include: forming a dielectric layer over the substrate, the dielectric layer may include a plurality of test regions; forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions; simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions from each other.Type: ApplicationFiled: October 30, 2014Publication date: May 5, 2016Inventors: Rudolf Zelsacher, Peter Irsigler, Erich Griebl, Manfred Pirker, Andreas Moser
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Publication number: 20160111415Abstract: An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.Type: ApplicationFiled: October 12, 2015Publication date: April 21, 2016Applicant: INFINEON TECHNOLOGIES AGInventors: Thomas Basler, Erich Griebl, Joachim Mahler, Daniel Pedone, Wolfgang Scholz, Philipp Seng, Peter Tuerkes, Stephan Voss
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Patent number: 9224806Abstract: A semiconductor device includes a semiconductor body and an edge termination structure. The edge termination structure comprises a first oxide layer, a second oxide layer, a semiconductor mesa region between the first oxide layer and the second oxide layer, and a doped field region comprising a first section in the semiconductor mesa region, and a second section in a region below the semiconductor mesa region. The second section overlaps the first and the second oxide layers in the region below the semiconductor mesa region.Type: GrantFiled: August 7, 2013Date of Patent: December 29, 2015Assignee: Infineon Technologies AGInventors: Stephan Voss, Alexander Breymesser, Hans-Joachim Schulze, Erich Griebl, Oliver Haeberlen, Andreas Moser
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Publication number: 20150236142Abstract: A cavity is formed in a first semiconductor layer that is formed on a semiconducting base layer. The cavity extends from a process surface of the first semiconductor layer to the base layer. A recessed mask liner is formed on a portion of a sidewall of the cavity distant to the process surface or a mask plug is formed in a portion of the cavity distant do the process surface. A second semiconductor layer is grown by epitaxy on the process surface. The second semiconductor layer spans the cavity.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Inventors: Johannes Georg Laven, Hans-Joachim Schulze, Anton Mauder, Erich Griebl
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Patent number: 9111989Abstract: A semiconductor device includes an IGBT having a semiconductor body including a transistor cell array in a first area. A junction termination structure is in a second area surrounding the transistor cell array at a first side of the semiconductor body. An emitter region of a first conductivity type is at a second side of the semiconductor body opposite the first side. The device further includes a diode. One of the diode anode and cathode includes the body region. The other one of the anode and the cathode includes a plurality of distinct first emitter short regions of a second conductivity type at the second side facing the transistor cell array, and at least one second emitter short region of the second conductivity type at the second side facing the junction termination structure. The at least one second emitter short region is distinct from the first emitter short regions.Type: GrantFiled: March 26, 2013Date of Patent: August 18, 2015Assignee: Infineon Technologies Austria AGInventors: Stephan Voss, Erich Griebl, Alexander Breymesser
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Publication number: 20150041962Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.Type: ApplicationFiled: August 9, 2013Publication date: February 12, 2015Inventors: Johannes Georg Laven, Maria Cotorogea, Hans-Joachim Schulze, Haybat Itani, Erich Griebl, Andreas Haghofer
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Publication number: 20150041946Abstract: A semiconductor device includes a semiconductor body and an edge termination structure. The edge termination structure comprises a first oxide layer, a second oxide layer, a semiconductor mesa region between the first oxide layer and the second oxide layer, and a doped field region comprising a first section in the semiconductor mesa region, and a second section in a region below the semiconductor mesa region. The second section overlaps the first and the second oxide layers in the region below the semiconductor mesa region.Type: ApplicationFiled: August 7, 2013Publication date: February 12, 2015Inventors: Stephan Voss, Alexander Breymesser, Hans-Joachim Schulze, Erich Griebl, Oliver Haeberlen, Andreas Moser
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Publication number: 20140291724Abstract: A semiconductor device includes an IGBT having a semiconductor body including a transistor cell array in a first area. A junction termination structure is in a second area surrounding the transistor cell array at a first side of the semiconductor body. An emitter region of a first conductivity type is at a second side of the semiconductor body opposite the first side. The device further includes a diode. One of the diode anode and cathode includes the body region. The other one of the anode and the cathode includes a plurality of distinct first emitter short regions of a second conductivity type at the second side facing the transistor cell array, and at least one second emitter short region of the second conductivity type at the second side facing the junction termination structure. The at least one second emitter short region is distinct from the first emitter short regions.Type: ApplicationFiled: March 26, 2013Publication date: October 2, 2014Inventors: Stephan Voss, Erich Griebl, Alexander Breymesser
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Patent number: 8815647Abstract: A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier.Type: GrantFiled: September 4, 2012Date of Patent: August 26, 2014Assignee: Infineon Technologies AGInventors: Ralf Otremba, Bernd Roemer, Erich Griebl, Fabio Brucchi
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Patent number: 8766430Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead.Type: GrantFiled: June 14, 2012Date of Patent: July 1, 2014Assignee: Infineon Technologies AGInventors: Ralf Otremba, Davide Chiola, Erich Griebl, Fabio Brucchi
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Publication number: 20140061669Abstract: A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier.Type: ApplicationFiled: September 4, 2012Publication date: March 6, 2014Applicant: Infineon Technologies AGInventors: Ralf Otremba, Bernd Roemer, Erich Griebl, Fabio Brucchi
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Publication number: 20130334677Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead.Type: ApplicationFiled: June 14, 2012Publication date: December 19, 2013Applicant: Infineon Technologies AGInventors: Ralf Otremba, Davide Chiola, Erich Griebl, Fabio Brucchi
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Patent number: 7821141Abstract: A semiconductor device including: a heat sink, a die on the heat sink, resin encapsulating the die, and a mounting aperture in the resin having at least a segment between the heat sink and a first end of the resin, wherein the thickness of the heat sink is no greater than 35% of the thickness of the device.Type: GrantFiled: February 22, 2008Date of Patent: October 26, 2010Assignee: Infineon Technologies AGInventors: Wae Chet Yong, Teck Sim Lee, Erich Griebl, Mario Feldvoss, Juergen Schredl
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Publication number: 20090212417Abstract: A semiconductor device including: a heat sink, a die on the heat sink, resin encapsulating the die, and a mounting aperture in the resin having at least a segment between the heat sink and a first end of the resin, wherein the thickness of the heat sink is no greater than 35% of the thickness of the device.Type: ApplicationFiled: February 22, 2008Publication date: August 27, 2009Inventors: Wae Chet Yong, Teck Sim Lee, Erich Griebl, Mario Feldvoss, Juergen Schredl
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Patent number: 7112868Abstract: An IGBT with monolithic integrated antiparallel diode has one or more emitter short regions forming the diode cathode in the region of the high-voltage edge. The p-type emitter regions of the IGBT have no emitter shorts. The counterelectrode of the diode exclusively comprises p-type semiconductor wells on the front side of the device. Particularly in applications, such as lamp ballast, in which the diode of the IGBT is firstly forward-biased, hard commutation is not effected and the current reversal takes place relatively slowly. The emitter short regions may be strips or points below the high-voltage edge. The horizontal bulk resistance is increased and the snapback effect is reduced without reducing the robustness in the edge region. In a second embodiment, the IGBT is produced using thin wafer technology and the thickness of the substrate defining the inner zone is less than 200 ?m. The thickness of the emitter region or of the emitter regions and short region(s) is less than 1 ?m.Type: GrantFiled: October 30, 2003Date of Patent: September 26, 2006Assignee: Infineon Technologies AGInventors: Armin Willmeroth, Hans-Joachim Schulze, Holger Huesken, Erich Griebl
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Publication number: 20040144992Abstract: An IGBT with monolithic integrated antiparallel diode has one or more emitter short regions forming the diode cathode in the region of the high-voltage edge. The p-type emitter regions of S the IGBT have no emitter shorts. The counterelectrode of the diode exclusively comprises p-type semiconductor wells on the front side of the device. Particularly in applications, such as lamp ballast, in which the diode of the IGBT is firstly forward-biased, hard commutation is not effected and the 10 current reversal takes place relatively slowly. The emitter short regions may be strips or points below the high-voltage edge. The horizontal bulk resistance is increased and the snapback effect is reduced without reducing the robustness in the edge region. In a second embodiment, the IGBT is produced 15 using thin wafer technology and the thickness of the substrate defining the inner zone is less than 200 &mgr;m. The thickness of the emitter region or of the emitter regions and short region(s) is less than 1 &mgr;m.Type: ApplicationFiled: October 30, 2003Publication date: July 29, 2004Inventors: Armin Willmeroth, Hans-Joachim Schulze, Holger Huesken, Erich Griebl
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Patent number: 6714397Abstract: A protection device for a Schottky diode is described. The protection device has a cascade circuit with at least two Si-PIN diodes provided parallel to the Schottky diode. The protection device protects against momentary over-current pulses reliably and without a high outlay in terms of cost and necessary materials for forming the protection device.Type: GrantFiled: August 5, 2002Date of Patent: March 30, 2004Assignee: Infineon Technologies AGInventors: Anton Mauder, Roland Rupp, Erich Griebl
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Publication number: 20030035259Abstract: A protection device for a Schottky diode is described. The protection device has a cascade circuit with at least two Si-PIN diodes provided parallel to the Schottky diode. The protection device protects against momentary over-current pulses reliably and without a high outlay in terms of cost and necessary materials for forming the protection device.Type: ApplicationFiled: August 5, 2002Publication date: February 20, 2003Inventors: Anton Mauder, Roland Rupp, Erich Griebl
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Patent number: D609191Type: GrantFiled: November 14, 2008Date of Patent: February 2, 2010Assignee: Infineon Technologies AGInventors: Mario Feldvoss, Erich Griebl, Teck Sim Lee, Juergen Schredl