Patents by Inventor Ernst H. A. Granneman
Ernst H. A. Granneman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080124470Abstract: Susceptors plates are formed having a minimum surface roughness. The wafer contact surfaces of the susceptor plates have a surface roughness Ra value of about 0.6 ?m or more. The contact surface is otherwise flat and lacking in large protrusions. In addition, the susceptors have a low transparency to more closely match the heat absorption properties of the supported wafer. Advantageously, heat transfer from the susceptors to the wafers is highly uniform. Thus, using these susceptors to support the wafers during high temperature semiconductor processing (e.g., at >1000° C.) results in no or few crystallographic slip lines being formed on the wafers.Type: ApplicationFiled: January 17, 2008Publication date: May 29, 2008Applicant: ASM INTERNATIONAL N.V.Inventors: Jannes Remco van den Berg, Ernst H.A Granneman
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Patent number: 7276774Abstract: A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no more than about a monolayer of material, capable of completely filling high aspect ratio trenches. Additionally, the trench-fill material composition can be tailored by processes described herein, particularly to match the coefficient of thermal expansion (CTE) to that of the surrounding substrate within which the trench is formed. Mixed phases of mullite and silica have been found to meet the goals of device isolation and matched CTE. The described process includes mixing atomic layer deposition cycles of aluminum oxide and silicon oxide in ratios selected to achieve the desired composition of the isolation material, namely on the order of 30% alumina and 70% silicon oxide by weight.Type: GrantFiled: June 14, 2004Date of Patent: October 2, 2007Assignee: ASM International N.V.Inventors: Ivo Raaijmakers, Pekka T. Soininen, Ernst H. A. Granneman
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Patent number: 7153772Abstract: A method of self-aligned silicidation involves interruption of the silicidation process prior to complete reaction of the blanket material (e.g., metal) in regions directly overlying patterned and exposed other material (e.g., silicon). Diffusion of excess blanket material from over other regions (e.g., overlying insulators) is thus prevented. Control and uniformity are insured by use of conductive rapid thermal annealing in hot wall reactors, with massive heated plates closely spaced from the substrate surfaces. Interruption is particularly facilitated by forced cooling, preferably also by conductive thermal exchange with closely spaced, massive plates.Type: GrantFiled: June 10, 2004Date of Patent: December 26, 2006Assignee: ASM International N.V.Inventors: Ernst H. A. Granneman, Vladimir Kuznetsov, Xavier Pages, Cornelius A. van der Jeugd
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Patent number: 7102235Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.Type: GrantFiled: December 15, 2003Date of Patent: September 5, 2006Assignee: ASM International N.V.Inventors: Ivo Raaijmakers, Suvi P. Haukka, Yille A. Saanila, Pekka J. Soininen, Kai-Erik Elers, Ernst H. A. Granneman
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Patent number: 7022627Abstract: A substrate undergoes a semiconductor fabrication process at different temperatures in a reactor without changing the temperature of the reactor. The substrate is held suspended by flowing gas between two heated surfaces of the reactor. Moving the two heated surfaces in close proximity with the substrate for a particular time duration heats the substrate to a desired temperature. The desired temperature is then maintained by distancing the heated surfaces from the substrate and holding the heated surface at the increased distance to minimize further substrate heating.Type: GrantFiled: October 31, 2003Date of Patent: April 4, 2006Assignee: ASM International N.V.Inventors: Ernst H. A. Granneman, Vladimir I. Kuznetsov, Xavier Pagès, Pascal G. Vermont
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Publication number: 20060060145Abstract: Susceptors plates are formed having a minimum surface roughness. The wafer contact surfaces of the susceptor plates have a surface roughness Ra value of about 0.6 ?m or more. The contact surface is otherwise flat and lacking in large protrusions. In addition, the susceptors have a low transparency to more closely match the heat absorption properties of the supported wafer. Advantageously, heat transfer from the susceptors to the wafers is highly uniform. Thus, using these susceptors to support the wafers during high temperature semiconductor processing (e.g., at>1000° C.) results in no or few crystallographic slip lines being formed on the wafers.Type: ApplicationFiled: March 15, 2005Publication date: March 23, 2006Inventors: Jannes Van Den Berg, Ernst H.A. Granneman
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Patent number: 6861334Abstract: A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no more than about a monolayer of material, capable of completely filling high aspect ratio trenches. Additionally, the trench-fill material composition can be tailored by processes described herein, particularly to match the coefficient of thermal expansion (CTE) to that of the surrounding substrate within which the trench is formed. Mixed phases of mullite and silica have been found to meet the goals of device isolation and matched CTE. The described process includes mixing atomic layer deposition cycles of aluminum oxide and silicon oxide in ratios selected to achieve the desired composition of the isolation material, namely on the order of 30% alumina and 70% silicon oxide by weight.Type: GrantFiled: June 21, 2001Date of Patent: March 1, 2005Assignee: ASM International, N.V.Inventors: Ivo Raaijmakers, Pekka T. Soininen, Ernst H. A. Granneman
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Patent number: 6831315Abstract: Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design.Type: GrantFiled: February 22, 2001Date of Patent: December 14, 2004Assignee: ASM International N.V.Inventors: Ivo Raaijmakers, Suvi P. Haukka, Ernst H. A. Granneman
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Publication number: 20040222490Abstract: A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no more than about a monolayer of material, capable of completely filling high aspect ratio trenches. Additionally, the trench-fill material composition can be tailored by processes described herein, particularly to match the coefficient of thermal expansion (CTE) to that of the surrounding substrate within which the trench is formed. Mixed phases of mullite and silica have been found to meet the goals of device isolation and matched CTE. The described process includes mixing atomic layer deposition cycles of aluminum oxide and silicon oxide in ratios selected to achieve the desired composition of the isolation material, namely on the order of 30% alumina and 70% silicon oxide by weight.Type: ApplicationFiled: June 14, 2004Publication date: November 11, 2004Inventors: Ivo Raaijmakers, Pekka T. Soininen, Ernst H.A. Granneman
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Publication number: 20040175586Abstract: Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design.Type: ApplicationFiled: March 3, 2004Publication date: September 9, 2004Inventors: Ivo Raaijmakers, Suvi P. Haukka, Ernst H. A. Granneman
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Patent number: 6780704Abstract: Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design.Type: GrantFiled: December 3, 1999Date of Patent: August 24, 2004Assignee: ASM International NVInventors: Ivo Raaijmakers, Suvi P. Haukka, Ernst H. A. Granneman
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Publication number: 20040142558Abstract: A deposition station allows atomic layer deposition (ALD) of films onto a substrate. The station comprises an upper and a lower substantially flat part between which a substrate is accommodated. The parts are positioned opposite each other and parallel to the substrate during processing. At least one of the parts is provided with a plurality of gas channels that allow at least two mutually reactive reactants to be discharged out of that part to the substrate. The discharge is configured to occur in a sequence of alternating, separated pulses for ALD. In addition, each part is preferably configured to be about 1 mm or less from the substrate to minimize the volume of the reaction chamber to increase the efficiency with which gases are purged from the chamber. Also, for each reactant, the upper and lower parts are preferably kept at a temperature outside of the window in which optimal ALD of that reactant occurs, thereby minimizing deposition of that reactant on deposition station surfaces.Type: ApplicationFiled: December 3, 2003Publication date: July 22, 2004Inventor: Ernst H. A. Granneman
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Publication number: 20040130029Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.Type: ApplicationFiled: December 15, 2003Publication date: July 8, 2004Inventors: Ivo Raaijmakers, Suvi P. Haukka, Yille A. Saanila, Pekka J. Soininen, Kai-Erik Elers, Ernst H.A. Granneman
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Patent number: 6727169Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.Type: GrantFiled: August 23, 2000Date of Patent: April 27, 2004Assignee: ASM International, N.V.Inventors: Ivo Raaijmakers, Suvi P. Haukka, Ville A. Saanila, Pekka J. Soininen, Kai-Erik Elers, Ernst H. A. Granneman
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Patent number: 6699783Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.Type: GrantFiled: November 21, 2002Date of Patent: March 2, 2004Assignee: ASM International N.V.Inventors: Ivo Raaijmakers, Pekka T. Soininen, Ernst H. A. Granneman, Suvi P. Haukka
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Patent number: 6686271Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.Type: GrantFiled: September 6, 2002Date of Patent: February 3, 2004Assignee: ASM International N.V.Inventors: Ivo Raaijmakers, Pekka T. Soininen, Ernst H. A. Granneman, Suvi P. Haukka
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Patent number: 6679951Abstract: The invention relates generally to the prevention of copper oxidation during copper anneal processes. In one aspect of the invention, copper oxidation is prevented by carrying out the anneal in the presence of one or more organic reducing agents.Type: GrantFiled: November 13, 2001Date of Patent: January 20, 2004Assignee: ASM Intenational N.V.Inventors: Pekka J. Soininen, Kai-Erik Elers, Ernst H. A. Granneman
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Publication number: 20030209200Abstract: A reactor for heat treatment of a substrate includes a process chamber within a substrate enclosing structure, and a support structure configured to position a substrate at a predetermined spacing between the upper part and the bottom part within the process chamber during processing. Streams of gas may lift the substrate from the support structure so that the substrate floats. A plurality of heating elements is associated with at least one of the upper part and the bottom part and are arranged to define heating zones. A controller controls the heating elements individually so that each heating zone is configured to have a predetermined temperature determined by the controller. The heating zones provide for a non-uniform heating laterally across the upper part and/or lower part adjacent the substrate.Type: ApplicationFiled: April 8, 2003Publication date: November 13, 2003Inventors: Vladimir Kuznetsov, Ernst H.A. Granneman
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Publication number: 20030134508Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.Type: ApplicationFiled: November 21, 2002Publication date: July 17, 2003Inventors: Ivo Raaijmakers, Pekka T. Soininen, Ernst H. A. Granneman, Suvi P. Haukka
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Publication number: 20030054631Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.Type: ApplicationFiled: September 6, 2002Publication date: March 20, 2003Inventors: Ivo Raaijmakers, Pekka T. Soininen, Ernst H. A. Granneman, Suvi P. Haukka