Abstract: An optoelectronic device including a substrate including first and second opposite surfaces and lateral electrical insulation elements extending in the substrate and delimiting first electrically-insulated semiconductor or conductive portions. The optoelectronic device includes, for each first portion, an assembly of light-emitting diodes electrically coupled to the first portion. The optoelectronic device includes an electrode layer covering all the light-emitting diodes, a protection layer covering the electrode layer, and walls extending in the protection layer and delimiting second portions surrounding or opposite the assemblies of light-emitting diodes. The walls contain at least one material from the group including air, a metal, a semiconductor material, a metal alloy, a partially transparent material, and a core made of an at least partially transparent material covered with an opaque or reflective layer.

Abstract: An optoelectronic device including semiconductor elements, each semiconductor element resting on a carrier through an aperture formed in a portion at least one first part of which is insulating and covers at least partially the carrier, the height of the aperture being larger than or equal to 100 nm and smaller than or equal to 3000 nm and the ratio of the height to the smallest diameter of the aperture being higher than or equal to 0.5 and lower than or equal to 10.

Abstract: A light-emitting device including a substrate at least partially doped with a first type of conductivity and including a face; light-emitting diodes each including at least one three-dimensional semiconducting element which is undoped or doped with the first type of conductivity and resting on the said face; and semiconducting regions forming photodiodes, at least partially doped with a second type of conductivity opposite to the first type of conductivity and extending in the substrate from the said face between at least some of the three-dimensional semiconducting elements, a portion of the substrate of first type of conductivity extending up to the said face at the level of each three-dimensional semiconducting element.

Abstract: A light-emitting device including a substrate at least partially doped with a first conductivity type and including a first surface and light-emitting diodes, each diode including at least one three-dimensional semiconductor element, which is or is not doped with the first conductivity type. The semiconductor elements rest on a continuous first portion of the first surface and at least one semiconductor region that forms a photodiode that is at least partially doped with a second conductivity type which is opposite the first conductivity type, and extends into the substrate from a second portion of the first surface that is separate from the first portion.

Abstract: An optoelectronic device including a semiconductor substrate including first and second opposing faces, a first set of first light-emitting diodes resting on a first portion of the substrate and including conical or frustoconical wire-like semiconductor elements, a first electrode covering each first light-emitting diode, a first conductive portion insulated from the substrate, extending through the substrate and connected to the first electrode; a second set of second light-emitting diodes resting on a second portion of the substrate and including conical or frustoconical wire-like semiconductor elements, a second electrode covering each second light-emitting diode, a second conductive portion insulated from the substrate and connected to the second electrode, and a first conductive element connecting the first conductive portion to the second portion of the substrate on the side of the second face.

Abstract: An optoelectronic device including a support having a first face; a first set of first light-emitting diodes having first wire-like, conical or frustoconical semiconductor elements, each resting on a second face of a first contact stud, each first contact stud including, in addition, a third face opposite the second face; and a first conductive layer connecting the first contact studs and extending at least over part of the second face or the third face of each first contact stud, the first conductive layer and/or the first contact studs resting on the support.

Abstract: An optoelectronic circuit for receiving a variable voltage having alternating increasing and decreasing phases. The optoelectronic circuit includes an alternating arrangement of resistive elements and light-emitting diode sets mounted in series. Each set contains two terminals. Each resistive element is inserted between two consecutive sets. The optoelectronic circuit includes, for each set among a plurality of said sets, a depletion mode metal oxide semiconductor field effect transistor, the drain and the source of which are coupled with the terminals of said set and the gate of which is coupled with one of the terminals of the next set. An additional resistive element is, for at least some of the transistors, coupled between the drain or the source of the transistor and one of the terminals of the set.

Abstract: An optoelectronic circuit for receiving a variable voltage having alternating increasing and decreasing phases. The optoelectronic circuit includes an alternating arrangement of resistive elements and light-emitting diode sets mounted in series. Each set contains two terminals. Each resistive element is inserted between two consecutive sets. The optoelectronic circuit includes, for each set among a plurality of said sets, a depletion mode metal oxide semiconductor field effect transistor, the drain and the source of which are coupled with the terminals of said set and the gate of which is coupled with one of the terminals of the next set. An additional resistive element is, for at least some of the transistors, coupled between the drain or the source of the transistor and one of the terminals of the set.

Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.

Abstract: An optoelectronic device including semiconductor elements, each semiconductor element resting on a carrier through an aperture formed in a portion at least one first part of which is insulating and covers at least partially the carrier, the height of the aperture being larger than or equal to 100 nm and smaller than or equal to 3000 nm and the ratio of the height to the smallest diameter of the aperture being higher than or equal to 0.5 and lower than or equal to 10.

Abstract: An optoelectronic device including a semiconductor substrate including first and second opposing faces, a first set of first light-emitting diodes resting on a first portion of the substrate and including conical or frustoconical wire-like semiconductor elements, a first electrode covering each first light-emitting diode, a first conductive portion insulated from the substrate, extending through the substrate and connected to the first electrode; a second set of second light-emitting diodes resting on a second portion of the substrate and including conical or frustoconical wire-like semiconductor elements, a second electrode covering each second light-emitting diode, a second conductive portion insulated from the substrate and connected to the second electrode, and a first conductive element connecting the first conductive portion to the second portion of the substrate on the side of the second face.

Abstract: An optoelectronic device including a support having a first face; a first set of first light-emitting diodes having first wire-like, conical or frustoconical semiconductor elements, each resting on a second face of a first contact stud, each first contact stud including, in addition, a third face opposite the second face; and a first conductive layer connecting the first contact studs and extending at least over part of the second face or the third face of each first contact stud, the first conductive layer and/or the first contact studs resting on the support.

Abstract: An optoelectronic device including a semiconductor substrate that is optionally doped with a first type of conductivity; a first semiconductor region that is electrically connected to the substrate, doped with the first type of conductivity or a second opposite type of conductivity and more strongly doped than the substrate; a first set of first light-emitting diodes resting on the first semiconductor region, the first light-emitting diodes comprising wire-like, conical or frustoconical semiconductor elements; and a conductive portion in contact with the first semiconductor region.

Abstract: Embodiments of the present invention provide a memory array of macro cells. Each macro cell comprises a storage element and a calibration element. The storage element and its corresponding calibration element are part of a common memory array within an integrated circuit, and therefore, are in close proximity to each other. The calibration element may store a parameter used to modify the threshold voltage of the storage element.

Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.

Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.

Abstract: A material stack including a semiconductor channel portion, a gate dielectric, a gate electrode, and a gate cap dielectric portion is formed on an insulator layer. The material stack is laterally enclosed by a dielectric spacer including a dielectric material that is different from the dielectric material of the insulator layer. The material stack and the dielectric spacer are undercut by an isotropic etch that removes the material of the insulator layer selective to the material of the dielectric spacer. A selective epitaxy process is employed to deposit a doped semiconductor material, which forms a source region and a drain region that are epitaxially in contact with the semiconductor channel portion. Metal semiconductor alloy portions can be formed on the source region and the drain region.

Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.

Abstract: A device includes a substrate; a shallow trench isolation (STI) region located in the substrate, the STI region comprising an STI material, and further comprising a recess in the STI material, the recess having a bottom and sides; a floating gate, wherein a portion of the floating gate is located on a side of the recess in the STI region and is separated from the substrate by a portion of the STI material; and a gate dielectric layer located over the floating gate, and a control gate located over the gate dielectric layer, wherein a portion of the control gate is located in the recess.

Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.