Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate; depositing a first material such that the first material overlaps the STI region and a portion of a top surface of the STI region is exposed; etching a recess in the STI region by a first etch, the recess having a bottom and sides; depositing a second material over the first material and on the sides and bottom of the recess in the STI region; and etching the first and second material by a second etch to form a floating gate of the device, wherein the floating gate extends into the recess.

Abstract: Embodiments of the present invention provide a memory array of macro cells. Each macro cell comprises a storage element and a calibration element. The storage element and its corresponding calibration element are part of a common memory array within an integrated circuit, and therefore, are in close proximity to each other. The calibration element may store a parameter used to modify the threshold voltage of the storage element.

Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.

Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate; depositing a first material such that the first material overlaps the STI region and a portion of a top surface of the STI region is exposed; etching a recess in the STI region by a first etch, the recess having a bottom and sides; depositing a second material over the first material and on the sides and bottom of the recess in the STI region; and etching the first and second material by a second etch to form a floating gate of the device, wherein the floating gate extends into the recess.

Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.

Abstract: A method of manufacturing at least one nanowire, the nanowire being parallel to its supporting substrate, the method including the formation on the supporting substrate of a structure comprising a bar and two regions, a first end of the bar being secured to one of the two regions and a second end of the bar being secured to the other region, the width of the bar being less than the width of the regions, the subjection of the bar to an annealing under gaseous atmosphere in order to transform the bar into a nanowire, the annealing being carried out under conditions allowing control of the sizing of the neck produced during the formation of the nanowire.

Abstract: The invention relates to a method for forming microcavities (118) of different depths in a layer (102) based on at least an amorphous or monocrystalline material, comprising at least the following steps in which: at least one shaft and/or trench is formed in the layer (102) so as to extend through one face (101) thereof, such that two sections of the shaft and/or the trench, in two different planes parallel to the face (101), are aligned in relation to one another along an alignment axis forming a non-zero angle with a normal to the plane of said face (101); and the layer (102) is annealed in a hydrogenated atmosphere so as to transform the shaft and/or trench into at least two microcavities (118).

Abstract: A method of forming a shallow trench isolation structure such that the shoulders of the wall formations on either side of the trench are rounded, whilst the walls and floor of the trench as well as the top surface of the formations on either side of the trench remain flat. This is achieved by anchoring the walls and floors with a partial gap fill, which may be achieved either by fully filling the gap and then reducing the level to below that of the formations on either side a the trench by polishing and etching steps, or by not completely filling the trench in the first place. The tops of the formations on either side of the trench meanwhile are protected by an oxide layer, which is pared back from the edge of the trench, for example by means of an isotropic etching process.

Abstract: A FET comprising an LDD region having a high overlap extension beneath the gate thereof and a pit region on the surface of the substrate immediately below the gate and entirely surrounded by said LDD region. The surface dopant concentration is in the vicinity of the gate corner so as to reduce the local field strength, and thereby decrease the GIDL, whilst keeping high overlap extension so a to maintain a high Ion current. More particularly a region under the gate corner but enclosed by the conventional LDD is counterdoped. Counter-doping of the LDD is performed with a sufficiently low energy, a specific dose and a low angle that the counter-doped region is enclosed into the LDD (at the substrate/gate-oxide interface and keeping high overlap extension between the gate oxide and the non-counter-doped LDD). As an optimum, the counter-doped region is under the gate corner. In that way, high Ion current is ensure with a overlap length is not altered.

Abstract: A method for forming a wire in a layer based on a monocrystalline or amorphous material. The method forms two trenches in the layer, crossing through one face of the layer, separated from each other by one portion of the layer, by an etching of the layer on which is arranged an etching mask, and anneals, under hydrogenated atmosphere, the layer, the etching mask being maintained on the layer during the annealing. The depths and widths of the sections of the two trenches, and the width of a section of the portion of the layer, are such that the annealing eliminates a part of the portion of the layer, the two trenches then forming a single trench in which a remaining part of the portion of the layer forms the wire.

Abstract: The invention relates to a method for forming microcavities (118) of different depths in a layer (102) based on at least an amorphous or monocrystalline material, comprising at least the following steps in which: at least one shaft and/or trench is formed in the layer (102) so as to extend through one face (101) thereof, such that two sections of the shaft and/or the trench, in two different planes parallel to the face (101), are aligned in relation to one another along an alignment axis forming a non-zero angle with a normal to the plane of said face (101); and the layer (102) is annealed in a hydrogenated atmosphere so as to transform the shaft and/or trench into at least two microcavities (118).

Abstract: A method for forming a wire in a layer based on a monocrystalline or amorphous material. The method forms two trenches in the layer, crossing through one face of the layer, separated from each other by one portion of the layer, by an etching of the layer on which is arranged an etching mask, and anneals, under hydrogenated atmosphere, the layer, the etching mask being maintained on the layer during the annealing. The depths and widths of the sections of the two trenches, and the width of a section of the portion of the layer, are such that the annealing eliminates a part of the portion of the layer, the two trenches then forming a single trench in which a remaining part of the portion of the layer forms the wire.

Abstract: A method of manufacturing at least one nanowire, the nanowire being parallel to its supporting substrate, the method comprising: the formation on the supporting substrate of a structure comprising a bar and two regions, a first end of the bar being secured to one of the two regions and a second end of the bar being secured to the other region, the width of the bar being less than the width of the regions, the subjection of the bar to an annealing under gaseous atmosphere in order to transform the bar into a nanowire, the annealing being carried out under conditions allowing control of the sizing of the neck produced during the formation of the nanowire.