Abstract: A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at the bottom of the trench whilst the nitride liner 50 protects the sidewalls 28 from oxidation. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.

Abstract: In semiconductor devices which include an insulated trench electrode (11) in a trench (20), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity (23) is provided between the bottom (25) of the trench electrode (11) and the bottom (27) of the trench (20) to reduce the dielectric coupling between the trench electrode (11) and the body portion at the bottom (27) of the trench in a compact manner. In power transistors, the reduction in dielectric coupling reduces switching power losses, and in Schottky diodes, it enables the trench width to be reduced.

Abstract: In semiconductor devices which include an insulated trench electrode (11) in a trench (20), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity (23) is provided between the bottom (25) of the trench electrode (11) and the bottom (27) of the trench (20) to reduce the dielectric coupling between the trench electrode (11) and the body portion at the bottom (27) of the trench in a compact manner. In power transistors, the reduction in dielectric coupling reduces switching power losses, and in Schottky diodes, it enables the trench width to be reduced.

Abstract: A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g.

Abstract: A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g.

Abstract: To avoid premature breakdown at the edge of the active area of RESURF trench-gate MOS device, an edge field plate (24) can be placed with a connection to the gate and a second spaced field plate (24) in the same trench (12). The gate trench network (12) could be either formed by hexagon unit cells or by square unit cells. Since the RESURF condition requires a small cell pitch, self-aligned processing could be used.

Abstract: In a cellular power MOSFET or other semiconductor device, a wide connection across the perimeter of an active device area (120) is replaced with a plurality of narrower conducting fingers (111). The fingers (11) are used as follows in providing a doped edge region (15a) that is required below the connection (110). Dopant (150,151) is implanted at spaces (112) between and beside the fingers (111) and is diffused to form a single continuous region (15a) extending beneath the fingers (111) and at the spaces (112) therebetween. This doped edge region (15a) may be, for example, a deep guard ring in an edge termination of a power MOSFET, or an extension of its channel-accommodating region (15). A trench-gate network (11) of the MOSFET can be connected by the conducting fingers to a gate bond pad and/or field plate (114).

Abstract: A vertical power transistor trench-gate semiconductor device has an active area (100) accommodating transistor cells and an inactive area (200) accommodating a gate electrode (25) (FIG. 6). While an n-type layer (14) suitable for drain regions still extends to the semiconductor body surface (10a), gate material (11) is deposited in silicon dioxide insulated (17) trenches (20) and planarised to the top of the trenches (20) in the active (100) and inactive (200) areas. Implantation steps then provide p-type channel-accommodating body regions (15A) in the active area (100) and p-type regions (15B) in the inactive area (200), and then source regions (13) in the active area (100). Further gate material (111) is then provided extending from the gate material (11) in the inactive area (200) and onto a top surface insulating layer (17B) for contact with the gate electrode (25).

Abstract: In semiconductor devices which include an insulated trench electrode (11) in a trench (20), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity (23) is provided between the bottom (25) of the trench electrode (11) and the bottom (27) of the trench (20) to reduce the dielectric coupling between the trench electrode (11) and the body portion at the bottom (27) of the trench in a compact manner. In power transistors, the reduction in dielectric coupling reduces switching power losses, and in Schottky diodes, it enables the trench width to be reduced.

Abstract: A field-effect semiconductor device, for example a MOSFET of the trench-gate type, comprises side-by-side device cells at a surface (10a) of a semiconductor body (10), and at least one drain connection (41) that extends in a drain trench (40) from the body surface (10a) to an underlying drain region (14a). A channel-accommodating region (15) of the device extends laterally to the drain trench (40). The drain trench (40) extends through the thickness of the channel-accommodating region (15) to the underlying drain region (14a), and the drain connection (41) is separated from the channel-accommodating region (15) by an intermediate insulating layer (24) on side-walls of the drain trench (40). A compact cellular layout can be achieved, with a significant proportion of the total cellular layout area accommodating conduction channels (12). The configuration in a discrete device avoids a need to use a substrate conduction path and so advantageously reduces the ON resistance of the device.

Abstract: A semiconductor body has source and drain regions (4 and 5) spaced apart by a body region (6) and both meeting a surface (3a) of the semiconductor body. A gate structure (7) is provided within a trench (8) for controlling a conduction channel in a conduction channel accommodation portion (60) of the body region (6) extending along at least side walls (8a) of the trench (8) and between the source and drain regions (4 and 5). A voltage-sustaining zone (600) consisting of first regions (6) of the same conductivity type as the source and drain regions interposed with second regions (62) of the opposite conductivity type is provided such that the first regions (61) provide a path for majority charge carriers to the drain region (5) when the device is conducting.

Abstract: A semiconductor body has source and drain regions (4 and 5; 4′ and 5′) spaced apart by a body region (6; 6′) and a drain drift region (50; 50′) and both meeting the same surface (3a) of the semiconductor body. An insulated gate structure (7; 70′; 700) is provided within a trench (80; 80′; 80″) extending in the semiconductor body. The gate structure has a gate conductive region (70b; 70′b; 70″b) separated from the trench by a dielectric layer (70a; 70′a) such that a conduction channel accommodation portion (60; 60′) of the body region extends along at least side walls (80a; 80′a; 80″a) of the trench and between the source (4; 4′) and drain drift (50; 50′) regions.

Abstract: To avoid premature breakdown at the edge of the active area of RESURF trench-gate MOS device, an edge field plate (24) can be placed with a connection to the gate and a second spaced field plate (24) in the same trench (12). The gate trench network (12) could be either formed by hexagon unit cells or by square unit cells. Since the RESURF condition requires a small cell pitch, self-aligned processing could be used.

Abstract: A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad.

Abstract: In a cellular power MOSFET or other semiconductor device, a wide connection across the perimeter of an active device area (120) is replaced with a plurality of narrower conducting fingers (111). The fingers (11) are used as follows in providing a doped edge region (15a) that is required below the connection (110). Dopant (150,151) is implanted at spaces (112) between and beside the fingers (111) and is diffused to form a single continuous region (15a) extending beneath the fingers (111) and at the spaces (112) therebetween. This doped edge region (15a) may be, for example, a deep guard ring in an edge termination of a power MOSFET, or an extension of its channel-accommodating region (15). A trench-gate network (11) of the MOSFET can be connected by the conducting fingers to a gate bond pad and/or field plate (114).

Abstract: The manufacture of a vertical power transistor trench-gate semiconductor device in which the source regions (13) are self-aligned to the trench-gate structures (20,17,11) including the steps of forming a mask (61) on a surface (10a) of a semiconductor body (10), using the mask (61) to form the trench-gate structures (20,17,11), then using the mask (61) to form U-shaped section layers (62A, 62B) of insulating material whose base portion (62B) provides a gate insulating layer on the gate material (11), then removing the mask (61) and forming spacers (64) against well-defined steps provided by the upright portions (62A) of the U-shaped section layers, then using the spacers (64) to form the source regions (13).

Abstract: The manufacture of a trench-gate semiconductor device, for example a power transistor or a memory device includes the steps of forming at a surface (10a) of a semiconductor body (10) a first mask (51) having a first window (51a), providing a thin layer of a second material (52) in the first window (51a), forming an intermediate mask (53A, 53B) of a third material having curved sidewalls and using the intermediate mask (53A, 53B) to form two L-shaped parts (52A, 52D and 52B, 52E) of the second material with a second window (52a) which is used to etch a trench-gate trench (20). The rectangular base portion (52D, 52E) of each L-shaped part ensures that the trench (20) is maintained narrow during etching. Narrow trenches are advantageous for low specific on-resistance and low RC delay in low voltage cellular trench-gate power transistors.

Abstract: A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of the body region (3a) between the source and drain regions. The device has one or more mesa structures (100) having end and side walls (100a to 100d). The body region (3a) extends between and meets at least the side walls (100c and 100d) of the mesa structure. The gate structure (7a, 7b) extends along and between the side walls such that the conduction channel accommodating portion (3b) extends along and between the side walls (100c and 100d). The source and drain regions (5 and 6) meet respective end walls (100a and 100b) of the mesa structure and/or its side walls (100c and 100d). At the mesa walls, a source electrode (S) contacts the source region (5) and a drain electrode (D) contacts the drain region (6). (FIGS.

Abstract: In the manufacture of a trench-gate semiconductor device, for example a MOSFET or an IGBT, a starting semiconductor body (10) has two top layers (13, 15) provided for forming the source and body regions. Gate material (11′) is provided in a trench (20) with a trench etchant mask (51, FIG. 2) still present so that the gate material (11′) forms a protruding step (30) from the adjacent surface (10a) of the semiconductor body, and a side wall spacer (32) is then formed in the step (30) to replace the mask (51). The source region (13) is formed self-aligned with the protruding trench-gate structure with a lateral extent determined by the spacer (32, FIG. 5), and the gate (11) is then provided with an insulating overlayer (18, FIG. 6).

Abstract: A vertical power transistor trench-gate semiconductor device has an active area (100) accommodating transistor cells and an inactive area (200) accommodating a gate electrode (25) (FIG. 6). While an n-type layer (14) suitable for drain regions still extends to the semiconductor body surface (10a), gate material (11) is deposited in silicon dioxide insulated (17) trenches (20) and planarised to the top of the trenches (20) in the active (100) and inactive (200) areas. Implantation steps then provide p-type channel-accommodating body regions (15A) in the active area (100) and p-type regions (15B) in the inactive area (200), and then source regions (13) in the active area (100). Further gate material (111) is then provided extending from the gate material (11) in the inactive area (200) and onto a top surface insulating layer (17B) for contact with the gate electrode (25).