Abstract: A method for testing semiconductor dies includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a first semiconductor die of the plurality of semiconductor dies by electrically connecting the test apparatus with the first contact element of the first semiconductor die and the contact location.

Abstract: A method for testing semiconductor dies includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a first semiconductor die of the plurality of semiconductor dies by electrically connecting the test apparatus with the first contact element of the first semiconductor die and the contact location.

Abstract: A method includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a semiconductor die by electrically connecting the test apparatus with the first contact element of the semiconductor die and the contact location.

Abstract: A method includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a semiconductor die by electrically connecting the test apparatus with the first contact element of the semiconductor die and the contact location.

Abstract: The invention provides a circuit apparatus having a circuit core module (100), a controller processor unit (102) for driving and addressing the circuit core module (100) and a data transmission unit (103a) for transmitting data between the circuit core module (100) and at least one external circuit module (110), provision being made of at least one further data transmission unit (103b-103n) that is of redundant design with respect to the data processing unit (103a), a data stream being changed over between the circuit core module (100) and the data transmission units (103a-103n) of multiply redundant design by means of a first changeover unit (201) and a data stream being changed over between the data transmission units (103a-103n) of multiply redundant design and the at least one external circuit module (110) by means of a second changeover unit (202).

Abstract: A method of testing a memory unit in a digital circuit includes storing a test pattern on a register of the digital circuit. The register is then selected by providing an activation signal to a selection unit. The memory unit is then tested with the test pattern stored in the register.

Abstract: The invention provides a device for monitoring electronic circuit units during an initialization phase. The device has at least one internal data line (103) for forwarding internal data (105) in the electronic circuit unit (101) and at least one data connection line (104) for outputting the internal data from the electronic circuit unit (101) and for inputting external data (106) into the electronic circuit unit (101). A changeover unit (102), which is intended to change over the data connection line (104) either to the internal data line (103) or to internal signal lines (113), and a combinational logic unit (111) for combining an initialization signal (109), which is provided by the electronic circuit unit (101) to be monitored, with an external changeover signal (108), which is supplied via a changeover signal input (107) of the electronic circuit unit (101) to be monitored, are also provided.

Abstract: The invention provides an electronic circuit apparatus having a plurality of electronic circuit units (101a-101n), a circuit board (102) and a connection unit (103), the circuit board (102) having a basic board element (200) and a plurality of additional board elements (201-204), the plurality of additional board elements (201-204) being connected to the basic board element (200) by means of connecting elements (301-304) and the circuit units being arranged on the additional board elements (201-204) in such a way that in each case identical signal propagation times are provided between the circuit units arranged on an additional board (201-204) and the connection unit (103).

Abstract: An integrated memory includes command terminals for receiving command signals in a normal operation and in a test operation of the memory, and also a signal terminal for receiving a further signal, which differs from the command signals. Registers store data patterns or data topologies for use in the test operation of the memory. A register decoder circuit serves for the selection of the registers, it being possible for inputs of the register decoder circuit to be connected to the command terminals and to the signal terminal for the purpose of selection of the registers in the test operation. The invention makes it possible, for the test operation, to address an increased number of registers without driving an additional external terminal pin. A method for testing the memory is also provided.

Abstract: A memory device with a multistage sense amplifier is disclosed. According to one aspect, a memory device has a memory cell array having at least one memory cell, at least one sense amplifier. Binary data signals read out from the memory cell are amplified and evaluated. The binary data signals can also be written back to the corresponding memory cell. Furthermore, an output unit for outputting the amplified and evaluated binary data signals and a coupling device between the memory cell array and the sense amplifier are provided. The coupling device has a preamplifier unit for preamplifying the data signals read out and a bridging unit for bridging the preamplifier unit in order to provide a writing back of the binary data signals to the memory cell of the memory cell array.

Abstract: The invention provides a test apparatus for testing a circuit unit (101) to be tested having a test system (100), a control bus (102) for transferring control data (106), an address bus (103) for transferring addressing data (107) and a data bus (104) for exchanging test data (108) between the test system (100) and the circuit unit (101) to be tested. A voltage generating device (200) connected between the test system (100) and the circuit unit (101) to be tested serves for generating a predeterminable operating voltage output signal (202, 202a-202n) for the voltage supply of the circuit unit (101) to be tested in a manner dependent on a control signal (211) that is provided by the test system (100) and fed via the control bus (102).

Abstract: The invention provides a test apparatus for testing a circuit unit to be tested. In one embodiment, a circuit unit incorporating aspects of the invention includes a data memory bank (106) for storing test mode data which are fed via an address control terminal (201) and with which the circuit unit (101) to be tested can be tested, provision being made of at least one test mode bank (104a-104n) for providing at least one test mode data set (204a-204n) and at least one activation signal (205a-205n), at least one register bank (103a-103n) and a transfer device for transferring a test mode data set (204a-204n) from a register bank (103a-103n) to the data memory bank (106) in a manner dependent on the activation signal (205a-205n).

Abstract: Apparatus and Method for Testing Circuit Units To Be Tested. According to one aspect, a test apparatus for testing circuit units to be tested, includes a nominal data production unit for production of a nominal data stream, a comparison device for comparison of an actual data stream which is emitted from the circuit unit to be tested as a function of the nominal data stream that is supplied with the nominal data stream; and a compression device for compression of an intermediate result signal which is emitted from the comparison device as a function of the comparison into a test result signal, with the intermediate result signal (108) which is emitted from the comparison device being temporarily stored in a buffer storage device with the intermediate result signal which is temporarily stored in a buffer storage device being read by means of a read unit.

Abstract: In a method for testing an electric circuit, a first circuit is produced by a first process sequence. A first signal is applied to the first circuit and a signal indicating if the first circuit is defective is generated by comparing the first signal with the first circuit output signal. Then, a second circuit is produced by a second process sequence which includes incorporating at least one intentional defect structure. The first signal is applied to the second circuit and a signal is generated by comparing the first signal with the second circuit output in response to the first signal. A modified signal is applied to the second circuit, until a comparison of the modified signal and the respective response of the second circuit indicates a defective second circuit. Information about the modified signal resulting in the indication of a defective second circuit is stored.

Abstract: A circuit configuration for testing a circuit using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve comparing actual data that are output by the circuit under test with prescribed nominal data in the test device. A combinational logic device for logically combining the sequentially output test results is provided such that result data indicate fault free operation of the circuit under test only if the actual data which are output match the prescribed nominal data in all of the sequentially performed test procedures. The result data is output via an addressing and control unit in the circuit under test.

Abstract: Electronic memory apparatus, and method for deactivating redundant bit lines or word lines An electronic memory apparatus (100) having a memory cell array (101), a column address decoding unit (102) for decoding a column addressing signal (105) and for actuating an addressed bit line in the memory cell array (101), a column redundancy activation unit (103) for activating a redundant bit line when a currently used bit line has been determined to be faulty during testing of the memory apparatus (100), a row address decoding unit (202) for decoding a row addressing signal (205) and for actuating an addressed word line in the memory cell array (101), and a row redundancy activation unit (203) for activating a redundant word line when a currently used word line has been determined to be faulty during testing of the memory apparatus (100).

Abstract: The invention provides a test device for testing circuit units (101a–101n) to be tested, having connecting units (106a–106n) for connecting the circuit units (101a–101n) to be tested to the test device, a test system (100) and an output unit (108) for outputting test result data, the test device having a determining unit (103) for determining those of the measurement data (110a–101n) which correspond for a predeterminable number of circuit units (101a–101n) to be tested, and for defining the corresponding measurement data (110a–110n) as the expected data (111); and comparison units (104a–104n) for comparing the measurement data (110a–110n) generated by the circuit units (101a–101n) to be tested in a manner dependent on the test data (112) written in with the expected data (111) in order to obtain comparison data (115a–115n).

Abstract: The invention relates to a method for verification of electronic circuit units (101) which are contained in a circuit apparatus (100) with the operating state of the electronic circuit unit (101) to be verified being read by means of the circuit apparatus (100), an identification key (102, HWID) being read from the electronic circuit unit (101) to be verified, a reference identification key (105) being transmitted (S5) to the circuit apparatus (100), the identification key (102) being compared (S6) with the reference identification key (105), and a message for a user being emitted (S6) when the identification key (102) read from the electronic circuit unit (101) to be verified does not match the transmitted reference identification key (105).

Abstract: The invention provides a test apparatus for testing circuit units (101a–101k) to be tested by means of a test system (100), having a connection device (102), tester channels (103a–103m) for connecting the test system (100) to the connection device (102) and receptacle units (104a–104k), having a number (n1, n2, . . . , nk) of circuit unit data channels dependent on the circuit units (101–101k) to be tested, provision being made of a changeover device (200) for changing over the tester channels (103a–103m) to the receptacle units (104a–104k), and it being possible to divide a number (m) of tester channels (103a–103m) between the number (n1, n2, . . . , nk) of circuit unit data channels in a predeterminable manner.

Abstract: In a method for testing an electric circuit, a first electric circuit is produced by a predetermined first process sequence. A data stream is applied to the first electric circuit and a signal being indicative if the first electric circuit is defective is generated by comparing the data stream with a data stream generated by the first electric circuit in response to the data stream. Then, a second electric circuit is produced by a predetermined second process sequence which includes incorporating intentionally at least one predetermined defect structure into the second electric circuit. The data stream is applied to the second electric circuit and a signal is generated by comparing the data stream with a data stream generated by the second electric circuit in response to the data stream.