Abstract: The invention provides a test apparatus for testing an electronic circuit unit to be tested. The test apparatus comprises a read-only memory for buffer-storing a test data stream read from the circuit unit to be tested in a manner dependent on a clock signal. The test apparatus further comprises a multiplexing unit for alternately outputting even data and odd data of the test data stream, and a driver device for driving the read-out test data stream to an output unit. Provision is made for a comparison device for bit by bit comparison of the even data and the odd data with one another and a blocking device for blocking the driver device if the read-out even data and the read-out odd data of the test data stream do not match.

Abstract: The invention provides a memory device having a memory cell array (100) having at least one memory cell (101), at least one sense amplifier (105), by means of which binary data signals read out from the memory cell (101) are amplified and evaluated, and can also be written back to the corresponding memory cell, and an output unit for outputting the amplified and evaluated binary data signals, provision further being made of a coupling device (200) between the memory cell array (100) and the sense amplifier (105), which coupling device comprises a preamplifier unit (201) for preamplifying the data signals read out and a bridging unit (202) for bridging the preamplifier unit in order to provide a writing back of the binary data signals to the memory cell of the memory cell array.

Abstract: The invention provides a test apparatus for testing a circuit unit (101) to be tested having a test system (100), a control bus (102) for transferring control data (106), an address bus (103) for transferring addressing data (107) and a data bus (104) for exchanging test data (108) between the test system (100) and the circuit unit (101) to be tested. A voltage generating device (200) connected between the test system (100) and the circuit unit (101) to be tested serves for generating a predeterminable operating voltage output signal (202, 202a-202n) for the voltage supply of the circuit unit (101) to be tested in a manner dependent on a control signal (211) that is provided by the test system (100) and fed via the control bus (102).

Abstract: The invention provides a method for controlling circuit functions of an electronic circuit apparatus, at least one input command signal (201), which is input via an external command bus (205), being buffer-stored in an input buffer (203) of the electronic circuit apparatus, the given input command signal (201) being processed in a processing unit (204) of the electronic circuit apparatus in such a manner that it is possible to control circuit functions of the circuit apparatus, and, before the input command signal (201) is forwarded to the processing unit (204), the input command signal (201) being monitored using a command control device (100) which is connected between the input buffer (203) and the processing unit (204). The invention also relates to an electronic circuit apparatus for carrying out the command monitoring method.

Abstract: The invention provides an electronic circuit apparatus having a plurality of electronic circuit units (101a-101n), a circuit board (102) and a connection unit (103), the circuit board (102) having a basic board element (200) and a plurality of additional board elements (201-204), the plurality of additional board elements (201-204) being connected to the basic board element (200) by means of connecting elements (301-304) and the circuit units being arranged on the additional board elements (201-204) in such a way that in each case identical signal propagation times are provided between the circuit units arranged on an additional board (201-204) and the connection unit (103).

Abstract: The invention provides a test apparatus for testing an electronic circuit device (101) to be tested by means of a test system (100), having an interface unit (102) for connecting the circuit device (101) to be tested to the test system (100), an address decoding unit (107) for decoding external addressing data (104) input by means of the test system (100) into internal addressing data (110, 112) and for addressing memory cells of a memory cell array (108) of the circuit device (101) to be tested with the internal addressing data (110, 112), and a memory data converter (115) for converting logical memory data (106), which are fed by the test system (100), into physical memory data (114). The memory data converter (115) carries out a conversion of the logical memory data (106) fed by the test system (100) into physical memory data (114) in a manner dependent on the internal addressing data (110, 112) of the circuit device (101) to be tested.

Abstract: Electronic memory apparatus, and method for deactivating redundant bit lines or word lines The invention provides an electronic memory apparatus (100) having a memory cell array (101), a column address decoding unit (102) for decoding a column addressing signal (105) and for actuating an addressed bit line in the memory cell array (101), a column redundancy activation unit (103) for activating a redundant bit line when a currently used bit line has been determined to be faulty during testing of the memory apparatus (100), a row address decoding unit (202) for decoding a row addressing signal (205) and for actuating an addressed word line in the memory cell array (101), and a row redundancy activation unit (203) for activating a redundant word line when a currently used word line has been determined to be faulty during testing of the memory apparatus (100).

Abstract: Monitoring device for monitoring internal signals during initialization of an electronic circuit unit The invention provides a device for monitoring electronic circuit units during an initialization phase. The device has at least one internal data line (103) for forwarding internal data (105) in the electronic circuit unit (101) and at least one data connection line (104) for outputting the internal data from the electronic circuit unit (101) and for inputting external data (106) into the electronic circuit unit (101). A changeover unit (102), which is intended to change over the data connection line (104) either to the internal data line (103) or to internal signal lines (113), and a combinational logic unit (111) for combining an initialization signal (109), which is provided by the electronic circuit unit (101) to be monitored, with an external changeover signal (108), which is supplied via a changeover signal input (107) of the electronic circuit unit (101) to be monitored, are also provided.

Abstract: The invention provides a test apparatus for testing a circuit unit to be tested. In one embodiment, a circuit unit incorporating aspects of the invention includes a data memory bank (106) for storing test mode data which are fed via an address control terminal (201) and with which the circuit unit (101) to be tested can be tested, provision being made of at least one test mode bank (104a-104n) for providing at least one test mode data set (204a-204n) and at least one activation signal (205a-205n), at least one register bank (103a-103n) and a transfer device for transferring a test mode data set (204a-204n) from a register bank (103a-103n) to the data memory bank (106) in a manner dependent on the activation signal (205a-205n).

Abstract: The invention provides a method for testing wafers (101) to be tested in a test device (100), in which the test device (100) can be calibrated, at least one calibration wafer (102) being automatically introduced into the test device (100) by means of a handling unit (103), calibration values of the test device (100) being determined by means of a control by a calibration sequence control unit (105), the calibration values determined being stored in a memory unit (106), the test device (100) being calibrated by means of the stored calibration values, the calibration wafer (102) being output from the calibrated test device (100), and at least one wafer (101) to be tested being introduced into the calibrated test device (100) by means of the handling unit (103) and being tested by a control by means of a test sequence control unit (104) in the calibrated test device (100), the stored calibration values being applied.

Abstract: The invention provides a memory apparatus having a memory module (100) (which has a memory bank (101a)), a controller processor unit, a control bus (104), an address bus (105) and a data bus (106) for interchanging data between the controller processor unit (102) and the memory module (100), the memory module also having at least one further memory bank (101b-101n) which can be activated by means of at least one bank selection signal (205a, 205b) which is provided by the controller processor unit (102) and is supplied via the control bus (104).

Abstract: The invention provides a test device for testing circuit units (101a-101n) to be tested, having connecting units (106a-106n) for connecting the circuit units (101a-101n) to be tested to the test device, a test system (100) and an output unit (108) for outputting test result data, the test device having a determining unit (103) for determining those of the measurement data (110a-101n) which correspond for a predeterminable number of circuit units (101a-101n) to be tested, and for defining the corresponding measurement data (110a-110n) as the expected data (111); and comparison units (104a-104n) for comparing the measurement data (110a-110n) generated by the circuit units (101a-101n) to be tested in a manner dependent on the test data (112) written in with the expected data (111) in order to obtain comparison data (115a-115n).

Abstract: An electronic calibration component for calibrating a tester device is described. The calibration component has a signal input, to which a tester channel to be calibrated can be connected, and a phase difference circuit. The phase difference circuit can be connected to the signal input and can be connected to a reference clock signal. As a result, a phase difference information item is determined between a cyclic signal applied to the signal input and the reference clock signal. The electronic calibration component also has an output device in order to output the phase difference information item. The latter is received by a tester device that can be connected to the calibration component via tester channels. The tester device has a delay device that is connected to the tester channel in order to delay signals to be transmitted on the tester channel on the basis of the phase difference information item.

Abstract: The invention provides a test apparatus for testing circuit units (101) to be tested by means of a test system, a circuit unit (101) to be tested having a register device (114), in which it is possible to store initialization data (115) that are fed by means of a storage signal (110), a control unit (102) for controlling a storage of the initialization data (115) and a switch-on unit (103) for switching on the at least one circuit unit (101) to be tested, a static storage device (201) for nonvolatile storage of the initialization data (115) that are fed by means of the storage signal (110) further being arranged in the circuit unit (101) to be tested.

Abstract: The invention provides a test apparatus for testing circuit units (101a-101k) to be tested by means of a test system (100), having a connection device (102), tester channels (103a-103m) for connecting the test system (100) to the connection device (102) and receptacle units (104a-104k), having a number (n1, n2, . . . , nk) of circuit unit data channels dependent on the circuit units (101-101k) to be tested, provision being made of a changeover device (200) for changing over the tester channels (103a-103m) to the receptacle units (104a-104k), and it being possible to divide a number (m) of tester channels (103a-103m) between the number (n1, n2, . . . , nk) of circuit unit data channels in a predeterminable manner.

Abstract: The invention provides a circuit apparatus having a circuit core module (100), a controller processor unit (102) for driving and addressing the circuit core module (100) and a data transmission unit (103a) for transmitting data between the circuit core module (100) and at least one external circuit module (110), provision being made of at least one further data transmission unit (103b-103n) that is of redundant design with respect to the data processing unit (103a), a data stream being changed over between the circuit core module (100) and the data transmission units (103a-103n) of multiply redundant design by means of a first changeover unit (201) and a data stream being changed over between the data transmission units (103a-103n) of multiply redundant design and the at least one external circuit module (110) by means of a second changeover unit (202).

Abstract: The invention provides a method for testing a memory unit (101) in a digital circuit (100), at least one test pattern (103) being stored in at least one register (102) of the digital circuit (100), at least one register being selected by means of an activation signal (106), the memory unit (101) to be tested being tested by means of the test pattern (103) stored in the at least one activated register (102), the at least one register (102) to be activated being selected by means of a selection unit (105), the activation signal (106) being fed to the selection unit.

Abstract: The invention provides a test apparatus for testing a circuit unit (113) to be tested which has a data input unit (104) for supplying a nominal data signal (117) to the circuit unit (113) to be tested, and a driver unit (108) for driving the actual data signal (105) (which is emitted from the circuit unit (113) to be tested as a function of the nominal data signal (117) supplied to it) to a data output unit (109) with at least one further signal, by means of which the serviceability of the circuit unit (113) to be tested can be determined being diverted to the data output unit (109).

Abstract: The invention provides a test apparatus for testing circuit units (117) to be tested, having a nominal data production unit (200) for production of a nominal data stream (201), a comparison device (103) for comparison of an actual data stream (100) (which is emitted from the circuit unit (117) to be tested as a function of the nominal data stream (201) that is supplied) with the nominal data stream (201); and a compression device (104) for compression of an intermediate result signal (108) (which is emitted from the comparison device (103) as a function of the comparison) into a test result signal (106), with the intermediate result signal (108) which is emitted from the comparison device (103) being temporarily stored in a buffer storage device (109) with the intermediate result signal (108) which is temporarily stored in a buffer storage device (109) being read by means of a read unit (111).

Abstract: A circuit configuration for testing a circuit that is under test using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve actual data that are output by the circuit under test on the basis of supplied test data are compared with prescribed nominal data in the test device. A combinational logic device for logically combining the sequentially output test results is provided such that result data indicate fault free operation of the circuit under test only if the actual data which are output match the prescribed nominal data in all of the sequentially performed test procedures. The result data is output via an addressing and control unit in the circuit under test.