Abstract: The present invention provides an apparatus for storing digital data, having: a multiplicity of memory cells (21) for storing digital data (14); an internal address generation device (15), connected to an address logic device (22), for managing and generating addresses; an internal control device (16), connected to the internal address generation device (15) and a control logic device (23), for controlling the address generation device (15) and the control logic device (23); a trigger input (11), connected to the internal address generation device (15), for clocking the internal address generation device (15); a control input (12), connected to the internal control device (16), for actuating the internal control device (16); and a data input/output (13) for interchanging digital data (14) on the basis of a trigger signal (11′) and a control signal (12′). The present invention likewise provides a method for storing digital data.

Abstract: An integrated memory includes command terminals for receiving command signals in-a normal operation and in a test operation of the memory, and also a signal terminal for receiving a further signal, which differs from the command signals. Registers store data patterns or data topologies for use in the test operation of the memory. A register decoder circuit serves for the selection of the registers, it being possible for inputs of the register decoder circuit to be connected to the command terminals and to the signal terminal for the purpose of selection of the registers in the test operation. The invention makes it possible, for the test operation, to address an increased number of registers without driving an additional external terminal pin. A method for testing the memory is also provided.

Abstract: The invention provides a method for testing wafers (101) to be tested in a test device (100), in which the test device (100) can be calibrated, at least one calibration wafer (102) being automatically introduced into the test device (100) by means of a handling unit (103), calibration values of the test device (100) being determined by means of a control by a calibration sequence control unit (105), the calibration values determined being stored in a memory unit (106), the test device (100) being calibrated by means of the stored calibration values, the calibration wafer (102) being output from the calibrated test device (100), and at least one wafer (101) to be tested being introduced into the calibrated test device (100) by means of the handling unit (103) and being tested by a control by means of a test sequence control unit (104) in the calibrated test device (100), the stored calibration values being applied.

Abstract: An electronic calibration component for calibrating a tester device is described. The calibration component has a signal input, to which a tester channel to be calibrated can be connected, and a phase difference circuit. The phase difference circuit can be connected to the signal input and can be connected to a reference clock signal. As a result, a phase difference information item is determined between a cyclic signal applied to the signal input and the reference clock signal. The electronic calibration component also has an output device in order to output the phase difference information item. The latter is received by a tester device that can be connected to the calibration component via tester channels. The tester device has a delay device that is connected to the tester channel in order to delay signals to be transmitted on the tester channel on the basis of the phase difference information item.