Patents by Inventor Esin Terzioglu
Esin Terzioglu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10713136Abstract: In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.Type: GrantFiled: September 22, 2017Date of Patent: July 14, 2020Assignee: Qualcomm IncorporatedInventors: Fahad Ahmed, Chulmin Jung, Sei Seung Yoon, Esin Terzioglu
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Publication number: 20190095295Abstract: In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.Type: ApplicationFiled: September 22, 2017Publication date: March 28, 2019Inventors: Fahad AHMED, Chulmin JUNG, Sei Seung YOON, Esin TERZIOGLU
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Patent number: 10049729Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may change a device operating voltage from a first voltage to a second voltage while the assist circuit is in a first state. The apparatus may also maintain the device operating voltage at the second voltage for a predetermined time. The apparatus may switch the assist circuit from the first state to a second state. The apparatus may adjust the device operating voltage to a third voltage after the predetermined time, wherein the second voltage is a voltage level between the first voltage and the third voltage. By transitioning the device operating voltage from the first voltage to the third voltage while at the same time preventing the assist circuit from entering particular read assist states, the apparatus may reduce a likelihood of read failures.Type: GrantFiled: September 19, 2017Date of Patent: August 14, 2018Assignee: QUALCOMM IncorporatedInventors: Esin Terzioglu, Sei Seung Yoon, Chulmin Jung, Bin Liang
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Patent number: 9984029Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.Type: GrantFiled: September 11, 2014Date of Patent: May 29, 2018Assignee: QUALCOMM IncorporatedInventors: Kern Rim, Stanley Seungchul Song, Xiangdong Chen, Raymond George Stephany, John Jianhong Zhu, Ohsang Kwon, Esin Terzioglu, Choh Fei Yeap
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Patent number: 9692448Abstract: An SoC integrated circuit package is provided in which the analog components of a SerDes for an SoC die in the SoC integrated circuit package are segregated into a SerDes interface die in the SoC integrated circuit package.Type: GrantFiled: September 22, 2016Date of Patent: June 27, 2017Assignee: QUALCOMM IncorporatedInventors: Xiaohua Kong, Mohamed Allam, Esin Terzioglu, Jose Gilberto Corleto Mena
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Patent number: 9542997Abstract: A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global data latch operable to receive a sensed data state from the local sense amplifier.Type: GrantFiled: October 7, 2015Date of Patent: January 10, 2017Assignee: Broadcom CorporationInventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
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Patent number: 9484110Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word lines. Each memory cell includes a high Vt transistor and a low Vt transistor.Type: GrantFiled: July 29, 2013Date of Patent: November 1, 2016Assignee: QUALCOMM IncorporatedInventors: Sei Seung Yoon, Chulmin Jung, Esin Terzioglu, Steven Mark Millendorf
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Patent number: 9331016Abstract: An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2?v2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g.Type: GrantFiled: July 22, 2014Date of Patent: May 3, 2016Assignee: QUALCOMM IncorporatedInventors: Xiangdong Chen, Ohsang Kwon, Esin Terzioglu, Hadi Bunnalim
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Patent number: 9252765Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.Type: GrantFiled: August 29, 2014Date of Patent: February 2, 2016Assignee: QUALCOMM IncorporatedInventors: Esin Terzioglu, Gregory Ameriada Uvieghara, Sei Seung Yoon, Balachander Ganesan, Anil Chowdary Kota
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Publication number: 20160027503Abstract: A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global data latch operable to receive a sensed data state from the local sense amplifier.Type: ApplicationFiled: October 7, 2015Publication date: January 28, 2016Inventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
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Patent number: 9214208Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.Type: GrantFiled: October 14, 2014Date of Patent: December 15, 2015Assignee: Mentor Graphics CorporationInventors: Esin Terzioglu, Gil I. Winograd
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Publication number: 20150301973Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.Type: ApplicationFiled: September 11, 2014Publication date: October 22, 2015Inventors: Kern RIM, Stanley Seungchul SONG, Xiangdong CHEN, Raymond George Stephany, John Jianhong ZHU, Ohsang KWON, Esin TERZIOGLU, Choh Fei YEAP
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Patent number: 9159385Abstract: A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global sense amplifier operable to receive a sensed data state from the local sense amplifier.Type: GrantFiled: January 14, 2014Date of Patent: October 13, 2015Assignee: Broadcom CorporationInventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
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Patent number: 9093995Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.Type: GrantFiled: May 29, 2013Date of Patent: July 28, 2015Assignee: QUALCOMM IncorporatedInventors: Kashyap Ramachandra Bellur, HariKrishna Chintarlapalli Reddy, Martin Saint-Laurent, Pratyush Kamal, Prayag Bhanubhai Patel, Esin Terzioglu
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Patent number: 9082481Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.Type: GrantFiled: October 1, 2014Date of Patent: July 14, 2015Assignee: QUALCOMM IncorporatedInventors: Esin Terzioglu, Nishith Desai, Rakesh Vattikonda, ChangHo Jung, Sei Seung Yoon
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Patent number: 9071239Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.Type: GrantFiled: March 13, 2013Date of Patent: June 30, 2015Assignee: QUALCOMM IncorporatedInventors: Chulmin Jung, Sei Seung Yoon, Esin Terzioglu, Hari Ananthanarayanan, Venugopal Boynapalli
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Publication number: 20150162062Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.Type: ApplicationFiled: October 14, 2014Publication date: June 11, 2015Applicant: MENTOR GRAPHICS CORPORATIONInventors: Esin Terzioglu, Gil I. Winograd
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Patent number: 9036446Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.Type: GrantFiled: October 29, 2012Date of Patent: May 19, 2015Assignee: QUALCOMM IncorporatedInventors: Esin Terzioglu, Changho Jung, Shahzad Nazar, Balachander Ganesan, Alex Dongkyu Park
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Publication number: 20150085554Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.Type: ApplicationFiled: October 1, 2014Publication date: March 26, 2015Inventors: Esin Terzioglu, Nishith Desai, Rakesh Vattikonda, ChangHo Jung, Sei Seung Yoon
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Patent number: 8958226Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.Type: GrantFiled: December 28, 2012Date of Patent: February 17, 2015Assignee: QUALCOMM IncorporatedInventors: Esin Terzioglu, Nishith Desai, Rakesh Vattikonda, ChangHo Jung, Sei Seung Yoon