Abstract: An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2?V2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g.

Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word liens. Each memory cell includes a high Vt transistor and a low Vt transistor.

Abstract: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.

Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract: A fuse-based memory includes a plurality of bit lines. Each bit lines couples to a corresponding plurality of fuses. The fuses couple to ground through corresponding access transistors. The memory is configured to precharge an accessed one of the bit lines and a reference one of the bit lines using a low voltage supply. In contrast, a resulting voltage difference between the accessed bit line and the reference bit line is sensed using a sense amplifier powered by a high voltage supply, wherein a high voltage supplied by the high power supply is greater than a low voltage supplied by the low voltage supply.

Abstract: Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods are disclosed. In one embodiment, the memory pre-decoder circuit includes a memory pre-decoder configured to pre-decode a memory address input within a memory pre-decode setup path to generate a pre-decoded memory address input. Additionally, a pulse latch is provided in the memory pre-decoder circuit outside of the memory pre-decode setup path. The pulse latch samples the pre-decoded memory address input based on a clock signal and generates a pre-decoded memory address output. As such, the memory pre-decode setup path sets up the pre-decoded memory address input prior to the clock signal for the pulse latch. In this manner, the pulse latch is configured to generate a pre-decoded memory address output without increasing setup times in the memory pre-decode setup path.

Abstract: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

Abstract: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.

Abstract: A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global sense amplifier operable to receive a sensed data state from the local sense amplifier.

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract: A memory includes at least first and second banks of single-port memory elements, a first local controller adapted to send read and write instructions to the first memory bank, and a second local controller adapted to send read and write instructions to the second memory bank. A global controller is configured to receive first and second memory addresses and a first indication of an operation to be performed at the first memory addresses and a second indication of an operation to be performed at the second memory address and to instruct the first local controller to perform the first indicated operation at the first memory address and to instruct the second local controller to perform the second indicated operation at the second memory address at the same time.