Abstract: A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having (n−1)-tier memory modules, which are coupled with (n)-tier sense amplifiers and (n)-tier decoders. Also provided are a single-ended sense amplifier having sample-and-hold reference, and a charge-share limited-swing-driver sense amplifier; an asynchronously-resettable decoder; a wordline decoder having row redundancy; a redundancy device having redundant memory cells operated by a redundancy controller; a diffusion replica delay circuit; a high-precision delay measurement circuit; and a data transfer bus circuit imposing a limited voltage swing on a data bus. Methods are provided for a write-after-read operation without an interposed precharge cycle, and write-after-write operation with an interposed precharge cycle are provided, either operation being completed in less than one memory access cycle.

Abstract: A high-precision delay measurement circuit delivers exceptionally accurate time measurement, for example, a half-gate delay. The high-precision delay measurement circuit has a multi-stage ring oscillator coupled with multiple oscillation signal detectors, which can be counters and signal edge detection circuits, which respectively count the number of oscillations by the circuit, and determine the extent to which a particular oscillation signal propagated within the oscillator. Some oscillation counters, particularly those disposed between the stages of the oscillator are dual-edge detection counters. The high precision delay measurement circuit can have a control signal output which can constrain a limited voltage swing signal.

Abstract: A limited swing driver with a pass transistor coupled between a memory cell and an associated bitline; an inverter, its output coupled to the gate of the pass transistor, and its input coupled with the memory cell. A memory node is formed at the juncture of the inverter input and the memory cell forming a memory node. The driver also includes a discharge transistor coupled between the memory node and ground. The discharge transistor is driven by an input on the discharge transistor gate. It is preferred that the discharge transistor being programmed to produce a limited swing voltage at the memory node. It is desirable that the limited swing voltage be less than about 350 mV, and it is preferable that the limited swing voltage be between about 300 mV and about 200 mV.

Abstract: A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus. In one embodiment, an inverter is coupled with a pMOS pass transistor and an nMOS discharge transistor, and the combination is coupled with a data bus. The discharge transistor and pass transistor can be programmed to provide a preselected bus operational characteristics. In another embodiment, multiple nMOS discharge transistors can be coupled to the data bus via the pass transistor, with each of the discharge transistors being selectively programmed to provide additional preselected bus operational characteristics, multiple, programmable discharge transistors, thus selectably imposing encoded and multilevel logic signals on the data bus. In another embodiment, a bidirectional data transfer bus circuit couples two data busses while imposing a limited, controlled voltage swing during the transfer.

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can includeselectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.