Abstract: A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) a controller (90) and a charge integrity estimating module (135). A series of successively larger operating voltages are transmitted to the cell from the voltage generator. The controller determines whether a predetermined value has been stored in the cell. The charge integrity estimating module detects the quantity of charge in the memory cell, for example, by using a sense amplifier (170).

Abstract: A non-volatile memory cell (10) includes a charge-storing node (16). An electrically insulating first layer (76) is coupled between the node and a source of a first voltage (22). An electrically insulating second layer (66) is coupled between the node and a source of a second voltage (20-21). The area of the first layer is smaller than the area of the second layer. A controller (90) is arranged to cause the first voltage to be greater than the second voltage so that charge is extracted from the node and is arranged to cause the second voltage to be greater than the first voltage so that charge is injected into the node.

Abstract: A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; hierarchically-coupled local and global row decoders; and a predecoding circuit coupled with selected global row decoders. The predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory access speed of the memory structure, allowing access to a memory cell at least twice during the memory access period, thereby providing dual-port functionality. A WRITE-AFTER-READ operation without a separate, interposed PRECHARGE cycle, is completed within one memory access cycle of the hierarchical memory structure. The method includes locally selecting the first memory location of a first datum; locally sensing the first datum (i.e.

Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

Abstract: The present invention relates to a system and method for equalizing the capacitance between at least two lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the lines using an algorithm. After determining the twisting pattern, the lines are twisted according to the pattern so that each of the lines runs along every other line for a same distance across the length of the bus.

Abstract: A method of implementing a diffusion replica delay circuit is provided in a device with a device capacitance and operational characteristics. A diffusion replica capacitor is coupled to the device and is capable of storing a predetermined replica charge representative of a selected device operational characteristic, and a diffusion replica transistor is coupled with the diffusion replica capacitor, and is coupled between the diffusion replica capacitor and a charge sink. The transistor is disposed to control the magnitude of the predetermined replica charge.

Abstract: The present invention relates to a system and method for providing distributed, highly configurable modular predecoding. The system includes a hierarchical memory structure, including a predecoder adapted to perform a first layer of address predecoding and at least one local predecoder interacting with the global predecoder and adapted to perform a second layer of address predecoding.

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can include selectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract: A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled. voltage swing on the associated data bus. In one embodiment, an inverter is coupled with a pMOS pass transistor and an nMOS discharge transistor, and the combination is coupled with a data bus. The discharge transistor and pass transistor can be programmed to provide a preselected bus operational characteristics. In another embodiment, multiple nMOS discharge transistors can be coupled to the data bus via the pass transistor, with each of the discharge transistors being selectively programmed to provide additional preselected bus operational characteristics, multiple, programmable discharge transistors, thus selectably imposing encoded and multilevel logic signals on the data bus. In another embodiment, a bidirectional data transfer bus circuit couples two data busses while imposing a limited, controlled voltage swing during the transfer.

Abstract: A decoder providing asynchronous reset, redundancy, or both. an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.

Abstract: A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet produces a residual offset signal value, which is substantially eliminated by the offset equalization network. The sense amplifier also can include an isolation circuit to isolate the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit is used to share charge between the bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the bit lines. The sense amplifier uses an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor.

Abstract: A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) and a controller (90). The controller is arranged to store a predetermined logical value in the cell by generating a series of the operating voltages beginning with the first voltage and continuing with successively larger operating voltages greater the first voltage. The voltages are transmitted to the cell from the voltage generator. After each transmittal of one of the series of operating voltages, the controller causes at least a portion of the charge stored in the cell to flow in the bit line. The controller determines whether the predetermined one of the logical values has been stored in the cell in response to the flow of charge. The controller terminates transmittal of the series of operating voltages to the cell in the event that the predetermined one of the logical states has been stored or in the event that one of the series of successively larger operating voltages equals the second voltage.

Abstract: A digital memory system (30) includes a memory cell (52) a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

Abstract: The present invention relates to a system and method for providing distributed, highly configurable modular predecoding. The system includes a hierarchical memory structure, including a predecoder adapted to perform a first layer of address predecoding and at least one local predecoder interacting with the global predecoder and adapted to perform a second layer of address predecoding.

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50) and a charge integrity estimating module 35. The module is operative during a first mode of operation to detect whether a quantity of the charge stored in the memory cell lies within the first range of values or the second range of values, is operative during a second mode of operation to detect whether the quantity of the charge lies within a third range of values comprising a subset of the first range of values and is operative during a third mode of operation to detect whether the quantity of the charge lies within a fourth range of values comprising a subset of the second range of values.

Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.