Patents by Inventor Essam Mina

Essam Mina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10832989
    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Barbara S. DeWitt, Essam Mina, B M Farid Rahman, Guoan Wang
  • Patent number: 10586752
    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Barbara S. DeWitt, Essam Mina, B M Farid Rahman, Guoan Wang
  • Publication number: 20200020612
    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Inventors: Barbara S. DeWITT, Essam MINA, B M Farid RAHMAN, Guoan WANG
  • Publication number: 20180286785
    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.
    Type: Application
    Filed: June 5, 2018
    Publication date: October 4, 2018
    Inventors: Barbara S. DeWITT, Essam MINA, B M Farid RAHMAN, Guoan WANG
  • Patent number: 10037931
    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 31, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Barbara S. DeWitt, Essam Mina, B M Farid Rahman, Guoan Wang
  • Publication number: 20170330821
    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.
    Type: Application
    Filed: August 4, 2017
    Publication date: November 16, 2017
    Inventors: Barbara S. DeWITT, Essam MINA, B M Farid RAHMAN, Guoan WANG
  • Patent number: 9780429
    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: October 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Barbara S. DeWitt, Essam Mina, B M Farid Rahman, Guoan Wang
  • Publication number: 20170110778
    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 20, 2017
    Inventors: Barbara S. DeWITT, Essam MINA, B M Farid RAHMAN, Guoan WANG
  • Patent number: 9553348
    Abstract: A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Barbara S. Dewitt, Essam Mina, BM Farid Rahman, Guoan Wang
  • Publication number: 20160226123
    Abstract: A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.
    Type: Application
    Filed: April 13, 2016
    Publication date: August 4, 2016
    Applicant: University of South Carolina
    Inventors: Barbara S. DEWITT, Essam MINA, BM Farid RAHMAN, Guoan WANG
  • Patent number: 9362606
    Abstract: A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: June 7, 2016
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, UNIVERISTY OF SOUTH CAROLINA
    Inventors: Barbara S. Dewitt, Essam Mina, B M Farid Rahman, Guoan Wang
  • Patent number: 9054157
    Abstract: A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Essam Mina, Guoan Wang, Wayne H. Woods, Jr.
  • Patent number: 9035719
    Abstract: A three dimensional (3D) branchline coupler using through silicon vias (TSV), methods of manufacturing the same and design structures are disclosed. The method includes forming a first waveguide structure in a first dielectric material. The method further includes forming a second waveguide structure in a second dielectric material. The method further includes forming through silicon vias through a substrate formed between the first dielectric material and the second dielectric material, which connects the first waveguide structure to the second waveguide structure.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Barbara S. Dewitt, Essam Mina, BM Farid Rahman, Guoan Wang, Wayne H. Woods, Jr.
  • Publication number: 20150054595
    Abstract: A three dimensional (3D) branchline coupler using through silicon vias (TSV), methods of manufacturing the same and design structures are disclosed. The method includes forming a first waveguide structure in a first dielectric material. The method further includes forming a second waveguide structure in a second dielectric material. The method further includes forming through silicon vias through a substrate formed between the first dielectric material and the second dielectric material, which connects the first waveguide structure to the second waveguide structure.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicants: University of South Carolina, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Barbara S. DEWITT, Essam MINA, BM Farid RAHMAN, Guoan WANG, Wayne H. WOODS, JR.
  • Publication number: 20150054592
    Abstract: A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicants: University of South Carolina, INTERNATIIONAL BUSINESS MACHINES CORPORATION
    Inventors: Barbara S. DEWITT, Essam MINA, BM Farid RAHMAN, Guoan WANG
  • Patent number: 8963657
    Abstract: On-chip, high performance, slow-wave coplanar waveguide with through-silicon via structures, method of manufacture and design structures for integrated circuits are provided herein. The method includes forming at least one ground plane layer in a substrate and forming a signal layer in the substrate, in a same plane layer as the at least one ground. The method further includes forming at least one metal filled through-silicon via between the at least one ground plane layer and the signal layer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Essam Mina, Guoan Wang, Wayne H. Woods, Jr.
  • Patent number: 8930871
    Abstract: A methodology for developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure is disclosed. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Essam Mina, Guoan Wang
  • Patent number: 8766748
    Abstract: On-chip high performance slow-wave microstrip line structures, methods of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and a signal layer provided in a different plane than the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness such that a height of the wide portion is different than a height of the narrow portion with respect to the at least one ground.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Essam Mina, Guoan Wang, Wayne H. Woods, Jr.
  • Patent number: 8766747
    Abstract: On-chip high performance slow-wave coplanar waveguide structures, method of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and a signal layer provided in a same plane as the at least one ground. The signal layer has at least one alternating wide portion and narrow portion. The wide portion extends toward the at least one ground.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Essam Mina, Guoan Wang
  • Patent number: 8760245
    Abstract: On-chip high performance slow-wave coplanar waveguide structures, method of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and signal layer provided in a same plane as the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness. The wide portion extends toward the at least one ground.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Essam Mina, Guoan Wang, Wayne H. Woods, Jr.