Abstract: A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface.

Abstract: A methodology for developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure is disclosed. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.

Abstract: A methodology is provided on developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.

Abstract: A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface.

Abstract: A single pole double throw (SPDT) semiconductor switch includes a series connection of a first transmitter-side transistor and a first reception-side transistor between a transmitter node and a reception node. Each of the two first transistors is provided with a gate-side variable impedance circuit, which provides a variable impedance connection between a complementary pair of gate control signals. Further, the body of each first transistor can be connected to a body bias control signal through a body-side variable impedance circuit. In addition, the transmitter node is connected to electrical ground through a second transmitter-side transistor, and the reception node is connected to electrical ground through a second reception-side transistor. Each of the second transistors can have a body bias that is tied to the body bias control signals for the first transistors so that switched-off transistors provide enhanced electrical isolation.

Abstract: T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar.

Abstract: A grounding plate and a transmission line are provided in a stack of dielectric material layers. First transmission line portions having a first width are alternately interlaced with second transmission line portions having a second width in the transmission line. The second width is greater than the first width so that inductance of the transmission line is increased relative to a transmission line having a fixed width. Metal fins may be provided between the grounding plate and the transmission line in the stack of the dielectric material layers. The metal fins may be grounded to the grounding plate to increase capacitance between the transmission line and the grounding plate. The increase in the inductance and the capacitance per unit length between the transmission line and the grounding plate is advantageously employed to provide a reduced phase velocity for electromagnetic signal transmitted through the transmission line. A design structure for the transmission line structure is provided.

Abstract: A single pole double throw (SPDT) semiconductor switch includes a series connection of a first transmitter-side transistor and a first reception-side transistor between a transmitter node and a reception node. Each of the two first transistors is provided with a gate-side variable impedance circuit, which provides a variable impedance connection between a complementary pair of gate control signals. Further, the body of each first transistor can be connected to a body bias control signal through a body-side variable impedance circuit. In addition, the transmitter node is connected to electrical ground through a second transmitter-side transistor, and the reception node is connected to electrical ground through a second reception-side transistor. Each of the second transistors can have a body bias that is tied to the body bias control signals for the first transistors so that switched-off transistors provide enhanced electrical isolation.

Abstract: A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface.

Abstract: An on-chip vertical coplanar waveguide with tunable characteristic impedance, a design structure, and a method of making the same. An on-chip transmission line includes a signal line, an upper ground line spaced apart from and above the signal line, and a lower ground line spaced apart from and below the signal line. The signal line, the upper ground line and the lower ground line are substantially vertically aligned in a dielectric material.

Abstract: On-chip high performance slow-wave coplanar waveguide structures, method of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and signal layer provided in a same plane as the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness. The wide portion extends toward the at least one ground.

Abstract: On-chip high performance slow-wave microstrip line structures, methods of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and a signal layer provided in a different plane than the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness such that a height of the wide portion is different than a height of the narrow portion with respect to the at least one ground.

Abstract: Branchline coupler structure using slow wave transmission line effect having both large inductance and large capacitance per unit length. The branchline coupler structure includes a plurality of quarter-wavelength transmission lines, at least one of which includes a high impedance arm and a low impedance arm. The high and low impedances are relative to each other. The high impedance arm includes a plurality of narrow cells and having an inductance of nL and a capacitance of C/n, and the low impedance arm includes a plurality of wide cells and having an inductance of L/n and capacitance of nC. The wide and narrow cells are relative to each other, and the wide and narrow cells are adjacent each other to form a signal layer having step discontinuous alternative widths.

Abstract: A methodology is provided on developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.

Abstract: On-chip high performance slow-wave coplanar waveguide structures, method of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and a signal layer provided in a same plane as the at least one ground. The signal layer has at least one alternating wide portion and narrow portion. The wide portion extends toward the at least one ground.

Abstract: Branchline coupler structure using slow wave transmission line effect having both large inductance and large capacitance per unit length. The branchline coupler structure includes a plurality of quarter-wavelength transmission lines, at least one of which includes a high impedance arm and a low impedance arm. The high and low impedances are relative to each other. The high impedance arm includes a plurality of narrow cells and having an inductance of nL and a capacitance of C/n, and the low impedance arm includes a plurality of wide cells and having an inductance of L/n and capacitance of nC. The wide and narrow cells are relative to each other, and the wide and narrow cells are adjacent each other to form a signal layer having step discontinuous alternative widths.

Abstract: An on-chip vertical coplanar waveguide with tunable characteristic impedance, a design structure, and a method of making the same. An on-chip transmission line includes a signal line, an upper ground line spaced apart from and above the signal line, and a lower ground line spaced apart from and below the signal line. The signal line, the upper ground line and the lower ground line are substantially vertically aligned in a dielectric material.

Abstract: T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar.

Abstract: A grounding plate and a transmission line are provided in a stack of dielectric material layers. First transmission line portions having a first width are alternately interlaced with second transmission line portions having a second width in the transmission line. The second width is greater than the first width so that inductance of the transmission line is increased relative to a transmission line having a fixed width. Metal fins may be provided between the grounding plate and the transmission line in the stack of the dielectric material layers. The metal fins may be grounded to the grounding plate to increase capacitance between the transmission line and the grounding plate. The increase in the inductance and the capacitance per unit length between the transmission line and the grounding plate is advantageously employed to provide a reduced phase velocity for electromagnetic signal transmitted through the transmission line. A design structure for the transmission line structure is provided.

Abstract: Methods are disclosed for determining a geometrical configuration of an interconnect structure of a test structure without cross-sectioning or optical measurements. In one embodiment, the method includes obtaining simulation data correlating capacitance data, resistance data and geometrical configuration data for a plurality of interconnect structures having different geometrical configurations; measuring a capacitance value and a resistance value from the interconnect structure of the test structure; and determining the geometrical configuration of the interconnect structure by comparing the capacitance value and the resistance value to the simulation data.