Abstract: A method, system and program product are disclosed that enable a netlist of an integrated circuit (IC) design for modeling of technology dependent back-end-of-line (BEOL) process variation. In one embodiment, the method includes obtaining a netlist of electrical elements (i.e., BEOL parasitic resistance and/or capacitance), the netlist including estimated electrical values for the electrical elements and geometric data for at least one of the electrical elements; determining variations of the electrical value for a selected electrical element based on the geometric data using a scaling methodology; and placing a model call in the netlist, the model call implementing the variations of electrical value for the selected electrical element. The revised netlist can be used to model the IC design and includes a scaling of electrical values without having to generate more than one netlist.

Abstract: A multi-band band pass filter, including: first and second multi-order asynchronous resonators connected to each other by a coupling resonator and connected to respective first and second matching resonators, the first matching resonator connected to a signal-in terminal and second matching resonator connected to a signal-out terminal respectively; a first reference resonator connected between the signal-in terminal and a reference-in terminal and a second reference resonator connected between the signal-out terminal and a reference-out terminal, the first multi-order asynchronous resonator connected between the first matching resonator and the coupling resonator to the first reference terminal and the second multi-order asynchronous resonator connected between the second matching resonator and the coupling resonator to the reference-out terminal, the reference-in terminal connected to the reference-out terminal; and a feedback resonator connected between the signal-in terminal and the signal-out terminal.

Abstract: A multi-band band pass filter, including: first and second multi-order asynchronous resonators connected to each other by a coupling resonator and connected to respective first and second matching resonators, the first matching resonator connected to a signal-in terminal and second matching resonator connected to a signal-out terminal respectively; a first reference resonator connected between the signal-in terminal and a reference-in terminal and a second reference resonator connected between the signal-out terminal and a reference-out terminal, the first multi-order asynchronous resonator connected between the first matching resonator and the coupling resonator to the first reference terminal and the second multi-order asynchronous resonator connected between the second matching resonator and the coupling resonator to the reference-out terminal, the reference-in terminal connected to the reference-out terminal; and a feedback resonator connected between the signal-in terminal and the signal-out terminal.

Abstract: A method, system and program product are disclosed that enable a netlist of an integrated circuit (IC) design for modeling of technology dependent back-end-of-line (BEOL) process variation. In one embodiment, the method includes obtaining a netlist of electrical elements (i.e., BEOL parasitic resistance and/or capacitance), the netlist including estimated electrical values for the electrical elements and geometric data for at least one of the electrical elements; determining variations of the electrical value for a selected electrical element based on the geometric data using a scaling methodology; and placing a model call in the netlist, the model call implementing the variations of electrical value for the selected electrical element. The revised netlist can be used to model the IC design and includes a scaling of electrical values without having to generate more than one netlist.

Abstract: Methods are disclosed for determining a geometrical configuration of an interconnect structure of a test structure without cross-sectioning or optical measurements. In one embodiment, the method includes obtaining simulation data correlating capacitance data, resistance data and geometrical configuration data for a plurality of interconnect structures having different geometrical configurations; measuring a capacitance value and a resistance value from the interconnect structure of the test structure; and determining the geometrical configuration of the interconnect structure by comparing the capacitance value and the resistance value to the simulation data.