Abstract: Embodiments of the present disclosure relate to a memory controller and operating method thereof. According to embodiments of the present disclosure, the memory controller may generate a fused linked list which includes information of a plurality of write commands received from a host and a plurality of synchronization commands requesting a synchronization operation, and control the synchronization operation for one or more of the plurality of write commands based on the fused linked list.

Abstract: An electronic device includes an external device configured to determine a first performance index on the basis of at least one of a power level and a temperature signal, to put the first performance index into a command, and to output the command. The electronic device also includes a storage component including a plurality of memory dies. The electronic device further includes a memory controller configured to provide the temperature signal to the external device at a set transmission period, and to control the storage component to process the command by simultaneously operating the number of memory dies corresponding to the first performance index as the command is received.

Abstract: A memory system, a memory controller, and an operating method of the memory system are provided. The memory system may include a memory device including a first type memory block and a second type memory block and a memory controller configured to determine, when receiving a command to set a read boost mode for the target logical address, whether the data corresponding to the target logical address can be copied from the first type memory block to the second type memory block, and copy the data corresponding to the target logical address from the first type memory block to the second type memory block.

Abstract: Embodiments of the present disclosure relate to a memory controller and operating method thereof. According to embodiments of the present disclosure, the memory controller may generate a fused linked list which includes information of a plurality of write commands received from a host and a plurality of synchronization commands requesting a synchronization operation, and control the synchronization operation for one or more of the plurality of write commands based on the fused linked list.

Abstract: A memory system that includes a system protection function implemented by using a double-map scheme, a memory controller, and operation methods thereof are disclosed. The memory system includes a memory device and a memory controller. The memory device includes a plurality of nonvolatile memory cells corresponding to a plurality of physical addresses respectively. The memory controller controls the memory device and uses a first map and a second map. The first map includes physical address mapping information based on a logical address for a physical address where first-type data is stored. The second map includes physical address mapping information based on a logical address for a physical address where second-type data is stored.

Abstract: A memory system may include: a nonvolatile memory device; and a controller suitable for generating first map information which maps physical addresses of the nonvolatile memory device to logical addresses received from a host, selecting some segments of the first map information as second map information, and outputting the second map information to the host, the controller may determine whether the second map information is updated, and may determine updated map segments as third map information, and the controller may output information to the host indicating the third map information corresponding to a command received from the host.

Abstract: A data processing system may include: a memory system comprising a memory device including a plurality of memory blocks; and a host suitable for dividing the memory device into a plurality of logical blocks, and including a plurality of segments each constituted by at least some of the plurality of logical blocks. The host may select a victim segment based on the number of the valid logical blocks corresponding to each of the memory blocks, and perform segment recycling on the victim segment, and one or more memory blocks may be invalidated by the segment recycling.

Abstract: Embodiments of the present disclosure relate to a memory controller and operating method thereof. According to embodiments of the present disclosure, the memory controller may generate a fused linked list which includes information of a plurality of write commands received from a host and a plurality of synchronization commands requesting a synchronization operation, and control the synchronization operation for one or more of the plurality of write commands based on the fused linked list.

Abstract: The present technology relates to a storage device. According to the present technology, a memory controller controlling a memory device including a plurality of memory blocks may include an operation controller and a lifetime information controller. The operation controller may control the memory device to receive a write request from a host and perform a write operation on a selected memory block among the plurality of memory blocks. The lifetime information controller may generate lifetime information including a lifetime level of the selected memory block based on an erase and write count of the selected memory block.

Abstract: A memory system may include: a nonvolatile memory device; and a controller suitable for generating first map information which maps physical addresses of the nonvolatile memory device to logical addresses received from a host, selecting some segments of the first map information as second map information, and outputting the second map information to the host, the controller may determine whether the second map information is updated, and may determine updated map segments as third map information, and the controller may output information to the host indicating the third map information corresponding to a command received from the host.

Abstract: A memory system may include: a nonvolatile memory device comprising a plurality of memory regions; and a controller in communication with the nonvolatile memory device to control operations of the nonvolatile memory device and configured to: receive a first write request including a first logical address and a second logical address; determine a duplicate physical address mapped to the second logical address; and selectively map the first logical address to the duplicate physical address based on a duplicate count corresponding to the duplicate physical address.

Abstract: Disclosed are a data processing system comprising: a memory system for providing a host with a memory map segment including map pieces; and the host for storing the memory map segment as a host map segment and converting a logical address into a physical address using the host map segment. The memory system stores changed map pieces in a map cache, inserts the changed map pieces in a response to a first command, and provides the host with the response. The host updates the host map segment based on the changed map pieces. When a read command includes a logical address and a physical address, the memory system accesses a memory device using the physical address of the read command according to whether the logical address of the read command is stored in the map cache.

Abstract: A memory controller for controlling a memory device which stores logical-to-physical (L2P) segments includes a map data storage and a map manager. The map data storage stores a plurality of physical-to-logical (P2L) segments including mapping information between a physical address of the memory device in which write data is to be stored and a logical address received from a host, in response to a write request received from the host. The map manager updates the L2P segments stored in the memory device, based on target P2L segments corresponding to a write command provided to the memory device, which have a higher priority than the other P2L segments among the plurality of P2L segments. Each of L2P segments includes mapping information between a logical address and a physical address of data stored in the memory device.

Abstract: A memory system may comprise: a memory device including a plurality of memory dies; and a controller including a first memory, Wherein the controller may store data segments of user data, corresponding to a plurality of commands received from a host, in the first memory, controls the memory device to sequentially store the data segments in the memory dies through interleaving, may update map segments of map data corresponding to storage of the data segments in the memory dies, may store the map segments in the first memory, controls the memory device to store the map segments stored in the first memory in the memory dies, and may assist the host in storing the map segments, stored in the first memory, in a second memory in the host.

Abstract: An electronic device includes an external device configured to determine a first performance index on the basis of at least one of a power level and a temperature signal, to put the first performance index into a command, and to output the command. The electronic device also includes a storage component including a plurality of memory dies. The electronic device further includes a memory controller configured to provide the temperature signal to the external device at a set transmission period, and to control the storage component to process the command by simultaneously operating the number of memory dies corresponding to the first performance index as the command is received.

Abstract: A memory system that includes a system protection function implemented by using a double-map scheme, a memory controller, and operation methods thereof are disclosed. The memory system includes a memory device and a memory controller. The memory device includes a plurality of nonvolatile memory cells corresponding to a plurality of physical addresses respectively. The memory controller controls the memory device and uses a first map and a second map. The first map includes physical address mapping information based on a logical address for a physical address where first-type data is stored. The second map includes physical address mapping information based on a logical address for a physical address where second-type data is stored.

Abstract: A memory system includes a memory device including a plurality of memory dies that store data, and a controller coupled to the plurality of memory dies through a plurality of channels, and suitable for generating and managing map data in which a logical address of a host is corresponding to a physical address of the memory device, wherein, when logical information on two or more consecutive logical addresses requested to be accessed and physical information on two or more consecutive physical addresses corresponding to the two or more consecutive logical addresses are inputted from the host, the controller sequentially performs access operations on the physical addresses corresponding to the received physical information.

Abstract: A data storage apparatus includes storage including a plurality of memory blocks and a controller configured to set an attribute of each of the memory blocks as a random memory block or a sequential memory block, and to manage validity of map data for data stored in each of the memory blocks using a map segment bitmap. The controller configures at least one memory block set by combining a set number of memory blocks, as a housekeeping event is triggered, and selects a victim block set from the at least one memory block set based on continuity of a logical address, or a number of valid map data, or both.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a host configured to generate and output a host command and a host address and to receive and store host map data, a controller configured to store map data, generate an internal command in response to the host command, and map the host address to an internal address based on the map data, and a memory device configured to perform an operation in response to the internal command and the internal address, wherein the controller is configured to load, when the map data corresponding to the host address is not stored in the controller, new map data into a map data storage area storing map data that is identical to the host map data.

Abstract: A memory system, a memory controller, and an operating method of the memory system are provided. The memory system may include a memory device including a first type memory block and a second type memory block and a memory controller configured to determine, when receiving a command to set a read boost mode for the target logical address, whether the data corresponding to the target logical address can be copied from the first type memory block to the second type memory block, and copy the data corresponding to the target logical address from the first type memory block to the second type memory block.