Patents by Inventor Eu-Joon BYUN

Eu-Joon BYUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Storage device and host device performing garbage collection operation
    Patent number: 11237961
    Abstract: A storage device includes a semiconductor memory device and a controller. The semiconductor memory device includes a plurality of memory blocks. The controller controls an operation of the semiconductor memory device. The controller includes a device garbage collection controller configured to select a victim memory block among the plurality of memory blocks, generate victim LBA information including a logical block address of a valid page in the selected victim memory block, and transfer the victim LBA information to a host device.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Memory system for utilizing a memory included in an external device
    Patent number: 11237973
    Abstract: A memory system includes a memory device and a controller. The memory device stores a piece of data in a location which is distinguished by a physical address. The controller generates map data, each piece of map data associating a logical address, inputted along with a request from an external device, with the physical address, selects a piece of map data among the map data based on a status regarding the piece of map data, and transfers selected map data to the external device.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Hye-Mi Kang, Eu-Joon Byun, Byung-Jun Kim, Seok-Jun Lee
  • Controller and data storage system having the same
    Patent number: 11237954
    Abstract: Provided herein may be a controller and a data storage system having the controller. The controller may include a mapping time generator configured to generate a first mapping time at which a logical block address and a physical block address are mapped to each other, an internal memory configured to store first address mapping information including an address map, and the first mapping time, a host interface configured to transmit the first address mapping information to a host, and receive second address mapping information from the host, and a central processing unit configured to generate the address map, store the first address mapping information in the internal memory, compare a second mapping time included in the second address mapping information with the first mapping time, and select a read mode based on a result of the comparison.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Hye Mi Kang, Eu Joon Byun
  • Memory system, memory controller and meta-information storage device
    Patent number: 11237976
    Abstract: Embodiments of the disclosure relate to a memory system, a memory controller and a meta-information storage device. By providing a memory device configured to store mapping information between a logical address and a physical address, a memory controller configured to control the memory device and control a memory area in which mapping segments including some of the mapping information are stored and a meta-information storage device configured to store meta-information on the memory area, it is possible to provide a memory system, a memory controller and a meta-information storage device capable of processing a command received from a host as quickly as possible even when an SPO occurs.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Hye-Mi Kang, Eu-Joon Byun
  • MEMORY CONTROLLER AND OPERATING METHOD THEREOF
    Publication number: 20220004332
    Abstract: A memory controller for controlling a memory device which stores logical-to-physical (L2P) segments includes a map data storage and a map manager. The map data storage stores a plurality of physical-to-logical (P2L) segments including mapping information between a physical address of the memory device in which write data is to be stored and a logical address received from a host, in response to a write request received from the host. The map manager updates the L2P segments stored in the memory device, based on target P2L segments corresponding to a write command provided to the memory device, which have a higher priority than the other P2L segments among the plurality of P2L segments. Each of L2P segments includes mapping information between a logical address and a physical address of data stored in the memory device.
    Type: Application
    Filed: January 13, 2021
    Publication date: January 6, 2022
    Inventors: Hye Mi KANG, Eu Joon BYUN
  • Controller, memory system and operating method of the controller
    Patent number: 11216384
    Abstract: Various embodiments generally relate to a semiconductor device, and more particularly, to a controller, a memory system and an operating method thereof. In accordance with an embodiment of the present disclosure, an operating method of a controller for controlling a nonvolatile memory device may include receiving a read command from a host; determining whether changed L2P map data corresponding to L2P map data included in the read command is registered in a dirty list; and performing, when the changed L2P map data is determined as registered in the dirty list, a read operation on the nonvolatile memory device based on the changed L2P map data among L2P map data included in a plurality of L2P segments.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Controller to control semiconductor memory device to perform garbage collection operation and method of operating the same
    Patent number: 11216363
    Abstract: A method of operating a controller configured to control a semiconductor memory device including a plurality of memory blocks may include selecting victim blocks that are targets for garbage collection among the plurality of memory blocks; determining whether data stored in valid pages included in each of the victim blocks includes sequential data; and performing a garbage collection operation on the victim blocks based on whether the data stored in the valid pages included in the each of victim blocks include sequential data.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Apparatus and method for transmitting map data in memory system
    Patent number: 11200178
    Abstract: An operation method of a memory system includes: searching for a valid physical address in memory map segments stored in the memory system, based on a read request from a host, a logical address corresponding to the read requests, and a physical address corresponding to the logical address and performing a read operation corresponding to the read request; caching some of the memory map segments in the host as host map segments based on a read count threshold indicating the number of receptions of the read request for the logical address; and adjusting the read count threshold based on a miss count indicating the number of receptions of the read request with no physical address, and a provision count indicating the number of times the memory map segment is cached in the host.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: December 14, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Memory controller having improved map data access performance and method of operating the same
    Patent number: 11194736
    Abstract: A memory controller may include a map cache configured to store one or more of a plurality of map data sub-segments respectively corresponding to a plurality of sub-areas included in each of the plurality of areas, and a map data manager configured to generate information about a map data sub-segment to be provided to a host and which is determined based on a read count for the memory device, and generate information about a map data segment to be deleted from the host and which is determined based on the read count for the memory device and a memory of the host.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Hye Mi Kang, Eu Joon Byun
  • APPARATUS AND METHOD FOR INCREASING OPERATION EFFICIENCY IN DATA PROCESSING SYSTEM
    Publication number: 20210365183
    Abstract: A data processing system may include: a memory system comprising a memory device including a plurality of memory blocks; and a host suitable for dividing the memory device into a plurality of logical blocks, and including a plurality of segments each constituted by at least some of the plurality of logical blocks. The host may select a victim segment based on the number of the valid logical blocks corresponding to each of the memory blocks, and perform segment recycling on the victim segment, and one or more memory blocks may be invalidated by the segment recycling.
    Type: Application
    Filed: January 25, 2021
    Publication date: November 25, 2021
    Inventor: Eu Joon BYUN
  • Memory system for flexible map block management and operating method thereof
    Patent number: 11169721
    Abstract: A memory system may include a memory device including a plurality of memory blocks; and a controller suitable for controlling the memory device. The controller may include a monitor suitable for monitoring valid data ratios of a first area and a second area and a processor suitable for comparing a first valid data ratio of the first area to a first threshold value, comparing a second valid data ratio of the second area to a second threshold value, and reallocating a target reserved memory block, which is allocated to the second area, to the first area according to the two comparison results.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • DATA PROCESSING SYSTEM INCLUDING PLURALITY OF MEMORY SYSTEMS
    Publication number: 20210342083
    Abstract: A data processing apparatus includes a first memory system including first and second interfaces and a first storage region, coupled to a host through the first interface, and configured to set a size of logical-to-physical (L2P) mapping of the first storage region to a first size unit; and a second memory system including a third interface coupled to the second interface to communicate with the first memory system, and configured to transmit capacity information for a second storage region included therein to the first memory system according to a request of the first memory system during an initial operation period, and set a size of logical-to-physical (L2P) mapping of the second storage region to a second size unit in response to a map setting command transmitted from the first memory system during the initial operation period.
    Type: Application
    Filed: October 30, 2020
    Publication date: November 4, 2021
    Inventor: Eu Joon BYUN
  • Controller, memory system and operating method thereof for controlling a non-volatile memory device during a sync-up operation
    Patent number: 11163696
    Abstract: Various embodiments generally relate to a semiconductor device, and more particularly, to a controller, a memory system and an operating method thereof. In an embodiment of the present disclosure, a controller for controlling a nonvolatile memory device may perform a sync-up operation of transmitting a logical-to-physical (L2P) map segment to a host to update the L2P map segment stored in a host memory included in the host when a map data changing event occurs, register the L2P map segment transmitted to the host and time information at which the sync-up operation is performed in a sync-up management list, calculate a sync-up period based on the time information, and perform the sync-up operation on an L2P map segment having a sync-up period greater than a threshold time, among L2P map segments registered in the sync-up management list.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Memory system and method of operating the same
    Patent number: 11163491
    Abstract: Provided herein is a memory system and a method of operating the memory system. The memory system may include: a memory device including a plurality of memory blocks; and a controller configured to control the memory device to perform a read operation in response to a host command, and configured to control a read reclaim operation based on a read count of each of the plurality of memory blocks. During the read reclaim operation, the controller may select a program mode of a target memory block depending on the amount of valid data read from a victim memory block, and control the memory device to store the valid data in the target memory block based on the selected program mode.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • ELECTRONIC DEVICE, DATA STORAGE DEVICE AND METHOD OF OPERATING THEREFOR
    Publication number: 20210326053
    Abstract: An electronic device may include a plurality of data storage devices including a master storage device and one or more slave storage devices. Each of the data storage devices comprises a storage configured to store data and a controller configured to control data input/output operations with respect to the corresponding storage. The controller of the master storage device receives device information including identification information, capacity information and physical configuration information from each of the slave storage devices, and the controller of the master storage device changes an electric power mode of at least one of the slave storage devices selected based on capacity margin of the master storage device and the device information.
    Type: Application
    Filed: September 16, 2020
    Publication date: October 21, 2021
    Inventor: Eu Joon BYUN
  • Memory system performing check pointing operation and operating method thereof
    Patent number: 11144406
    Abstract: A memory system includes a plurality of dies including a plurality of memory blocks, each die including a first region and a second region; and a controller which includes a memory storing plural pieces of check point information and a processor, wherein the processor includes: a check point manager suitable for performing a check pointing operation by programming identification information and check point information on the plurality of memory blocks, according to the size of the plural pieces of; and a recovery manager suitable for resuming an operation stopped due to a sudden power-off (SPO) by using last check point information and last identification information, which are programmed last in memory blocks in each of the dies when the SPO occurs.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Memory system and operation method thereof
    Patent number: 11144449
    Abstract: An operation method of a memory system includes a memory device including plural level memory cells. The operation method includes allocating a physical address according to a physical address allocation scheme which is determined based on an attribute of a write command; and performing a write operation on the allocated physical address.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Apparatus and method for transmitting map data in memory system
    Patent number: 11144478
    Abstract: An operation method of a memory system includes: searching for a valid physical address in memory map segments stored in the memory system, based on a read request from a host, a logical address corresponding to the read requests, and a physical address corresponding to the logical address and performing a read operation corresponding to the read request; caching some of the memory map segments in the host as host map segments based on a read count threshold indicating the number of receptions of the read request for the logical address; and adjusting the read count threshold based on a miss count indicating the number of receptions of the read request with no physical address, and a provision count indicating the number of times the memory map segment is cached in the host.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Memory system using available bad block based on data storage reliability and operating method thereof
    Patent number: 11144246
    Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks and a controller configured to control the nonvolatile memory device. The controller determines, as an available bad block, a memory block having data storage reliability equal to or greater than a first reference value, included in the plurality of memory blocks, determines write data to be stored in the nonvolatile memory device as first data which is required for the memory system to normally operate or second data which does not correspond to the first data, and allocate the write data determined as the second data to the available bad block. The nonvolatile memory device performs a write operation of storing the second data in the available bad block.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Memory controller and method of operating the same
    Patent number: 11139020
    Abstract: A memory controller includes a mapping data controller configured to generate extended mapping data including mapping information and an additional field in response to an extended mapping data request received from a host and to generate data generation information indicating that the extended mapping data has been generated, wherein the mapping information indicates a mapping relationship between a logical block address and a physical block address and a bitmap information generator configured to receive the data generation information and generate bitmap information. The bitmap information may include information for changing a bit value corresponding to a mapping data group including the extended mapping data, among bit values included in a bitmap, to indicate the extended mapping data, and the mapping data group may include a plurality of pieces of mapping data.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventors: Eu Joon Byun, Jea Young Zhang