Patents by Inventor Eugene A. Fitzgerald

Eugene A. Fitzgerald has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10418273
    Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 17, 2019
    Assignees: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao, Yiding Lin, Jurgen Michel
  • Patent number: 10406721
    Abstract: Features for formliners to form a decorative pattern in a curable material and methods of using the same are disclosed. An improved formliner is disclosed with substantially seamlessly connecting components that reduces the need for using adhesives for interconnecting a plurality of formliners in a pattern. Further, the formliner is configured to reduce and/or substantially eliminate visible seams in order to create a more natural appearance in a finished product of the curable material.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: September 10, 2019
    Assignee: PRIME FORMING & CONSTRUCTION SUPPLIES, INC.
    Inventors: Edward Daniel Fitzgerald, Brian Eugene Sheehan
  • Publication number: 20190168415
    Abstract: A formliner, sheet, system, and methods of use and manufacture are provided in order to provide a product that can minimize and/or eliminate visible seaming between interconnected formliners during fabrication of a pattern on a curable material. In some embodiments, the formliner can comprise raised sections that define interrelated inner and outer dimensions. Thus, a plurality of formliners can be interconnected by overlaying raised sections thereof. Further, the formliner can comprise one or more detents and one or more protrusions to enable engagement between interconnected formliners without requiring adhesives. In this manner, formliners can be interconnected in a nested manner such that visible seaming between the interconnected formliners is reduced and/or eliminated.
    Type: Application
    Filed: November 26, 2018
    Publication date: June 6, 2019
    Inventors: Edward Daniel Fitzgerald, Brian Eugene Sheehan
  • Publication number: 20190074214
    Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.
    Type: Application
    Filed: October 11, 2016
    Publication date: March 7, 2019
    Applicants: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao, Yiding Lin, Jurgen Michel
  • Publication number: 20190051516
    Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.
    Type: Application
    Filed: January 20, 2017
    Publication date: February 14, 2019
    Inventors: Kwang Hong Lee, Li Zhang, Soo Jin Chua, Eng Kian Kenneth Lee, Eugene A. Fitzgerald, Chuan Seng Tan
  • Publication number: 20190035628
    Abstract: Method and structure for reducing substrate fragility. In one embodiment, a substrate for metamorphic epitaxy of a material film is provided, the substrate comprising a passivation layer defining a growth window for the material film on a deposition surface of the substrate, the growth window being laterally spaced from an edge of the substrate.
    Type: Application
    Filed: January 19, 2017
    Publication date: January 31, 2019
    Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NATIONAL UNIVERSITY OF SINGAPORE, NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Li ZHANG, Kwang Hong LEE, Shuyu BAO, Eng Kian Kenneth LEE, Eugene A. FITZGERALD, Soo Jin CHUA, Chuan Seng TAN
  • Patent number: 10164015
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Publication number: 20180330982
    Abstract: A method of manufacturing a hybrid substrate is disclosed, which comprises: bonding a first semiconductor substrate to a first combined substrate via at least one layer of dielectric material to form a second combined substrate, the first combined substrate includes a layer of III-V compound semiconductor and a second semiconductor substrate, the layer of III-V compound semiconductor arranged intermediate the layer of dielectric material and second semiconductor substrate; removing the second semiconductor substrate from the second combined substrate to expose at least a portion of the layer of III-V compound semiconductor to obtain a third combined substrate; and annealing the third combined substrate at a temperature about 250° C. to 1000° C. to reduce threading dislocation density of the layer of III-V compound semiconductor to obtain the hybrid substrate.
    Type: Application
    Filed: November 10, 2016
    Publication date: November 15, 2018
    Applicants: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao, Eng Kian Kenneth Lee, David Kohen
  • Publication number: 20180277629
    Abstract: A method of manufacturing a substrate with reduced threading dislocation density is disclosed, which comprises: (i) at a first temperature, forming a first layer of wafer material on a semiconductor substrate, the first layer arranged to be doped with a first concentration of at least one dopant that is different to the wafer material; and (ii) at a second temperature higher than the first temperature, forming a second layer of the wafer material on the first layer to obtain the substrate, the second layer arranged to be doped with a progressively decreasing concentration of the dopant during formation, the doping configured to be decreased from the first concentration to a second concentration. The wafer material and dopant are different to silicon. A related substrate is also disclosed.
    Type: Application
    Filed: September 2, 2016
    Publication date: September 27, 2018
    Applicants: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao
  • Publication number: 20180254197
    Abstract: A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 6, 2018
    Applicants: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Eng Kian Kenneth Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Viet Cuong Nguyen
  • Patent number: 10049947
    Abstract: A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: August 14, 2018
    Assignees: Massachusetts Institute of Technology, Nanyang Technological University
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Eng Kian Kenneth Lee
  • Patent number: 10049916
    Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding (102) the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing (104) the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing (106) the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 14, 2018
    Assignees: Massachusetts Institute of Technology, Nanyang Technological University
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Yew Heng Tan, Gang Yih Chong, Eugene A. Fitzgerald, Shuyu Bao
  • Patent number: 10050145
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • Publication number: 20180197954
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Application
    Filed: March 1, 2018
    Publication date: July 12, 2018
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Patent number: 9923057
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Publication number: 20170271201
    Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding (102) the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing (104) the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing (106) the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.
    Type: Application
    Filed: May 22, 2015
    Publication date: September 21, 2017
    Applicants: Massachusetts Institute of Technology, Nanyang Technological University
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Yew Heng Tan, Gang Yih Chong, Eugene A. Fitzgerald, Shuyu Bao
  • Publication number: 20170200648
    Abstract: A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.
    Type: Application
    Filed: July 6, 2015
    Publication date: July 13, 2017
    Applicants: Massachusetts Institute of Technology, Nanyang Technological University
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Eng Kian Kenneth Lee
  • Publication number: 20170179285
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • Publication number: 20170117176
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Application
    Filed: January 6, 2017
    Publication date: April 27, 2017
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 9601623
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald