Patents by Inventor Eugene A. Fitzgerald

Eugene A. Fitzgerald has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8604330
    Abstract: In various embodiments, an array of discrete solar cells with associated devices such as bypass diodes is formed over a single substrate. In one instance, a method of forming a solar-cell array with integrated bypass diodes comprising: providing a semiconductor substrate, a first cell comprising a SiGe p-n junction or SiGe p-i-n junction, one or more second cells each comprising a III-V semiconductor p-n junction or III-V semiconductor p-i-n junction; forming a bypass diode that is discrete and laterally separate from its associated solar cell and comprises an unremoved portion of the first cell, the formation comprising removing an unremoved portion of the one or more second cells thereover.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: December 10, 2013
    Assignee: 4Power, LLC
    Inventors: John J. Hennessy, Andrew C. Malonis, Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
  • Patent number: 8586452
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • Patent number: 8436336
    Abstract: The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: May 7, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Minjoo L. Lee, Christopher W. Leitz, Eugene A. Fitzgerald
  • Patent number: 8344355
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Patent number: 8187379
    Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: May 29, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Publication number: 20120125203
    Abstract: Water purification system comprising filtration media sized with respect to each other to allow a first contaminant in the water to saturate the first medium with a delay prior to saturation of the second medium with a second contaminant.
    Type: Application
    Filed: August 22, 2011
    Publication date: May 24, 2012
    Applicant: THE WATER INITIATIVE, LLC
    Inventors: Eugene A. Fitzgerald, Ya-Hong Xie, Thomas Langdo, Richard Renjilian, Carl V. Thompson
  • Publication number: 20120086047
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 12, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew Currie, Anthony Lochtefeld, Richard Hammond, Eugene Fitzgerald
  • Patent number: 8120060
    Abstract: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure also includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based electronic device comprising an element including at least a portion of the monocrystalline silicon layer.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: February 21, 2012
    Assignee: Massachusetts Institute of Technology
    Inventor: Eugene A. Fitzgerald
  • Patent number: 8106380
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: January 31, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene Fitzgerald
  • Publication number: 20110318893
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Application
    Filed: September 7, 2011
    Publication date: December 29, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • Patent number: 8063413
    Abstract: A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: November 22, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Yu Bai, Minjoo L. Lee, Eugene A. Fitzgerald
  • Patent number: 8063397
    Abstract: Semiconductor light-emitting structures are shown on engineered substrates having a graded composition. The composition of the substrate may be graded to achieve a lattice constant on which a yellow-green light-emitting semiconductor material may be disposed. In some embodiments, the structure may be substantially free of aluminum.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 22, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Michael J. Mori, Eugene A. Fitzgerald
  • Patent number: 8026534
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: September 27, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 8012592
    Abstract: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a semiconductor structure includes a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The semiconductor structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region, a monocrystalline silicon layer disposed over the insulating layer in the first region, and a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region. The second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: September 6, 2011
    Assignee: Massachuesetts Institute of Technology
    Inventor: Eugene A. Fitzgerald
  • Publication number: 20110177681
    Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Application
    Filed: March 29, 2011
    Publication date: July 21, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Publication number: 20110143495
    Abstract: In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 16, 2011
    Inventors: Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
  • Publication number: 20110132445
    Abstract: In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover.
    Type: Application
    Filed: May 28, 2010
    Publication date: June 9, 2011
    Inventors: Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
  • Patent number: 7955435
    Abstract: A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: June 7, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Publication number: 20110124146
    Abstract: In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover.
    Type: Application
    Filed: May 28, 2010
    Publication date: May 26, 2011
    Inventors: Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
  • Publication number: 20110095363
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Application
    Filed: December 30, 2010
    Publication date: April 28, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew Currie, Anthony Lochtefeld, Richard Hammond, Eugene Fitzgerald