Abstract: Embodiments are directed to a method of forming a magnetic stack arrangement of a laminated magnetic inductor having a high frequency peak quality factor (Q). A first magnetic stack is formed having one or more magnetic layers alternating with one or more insulating layers in a first inner region of a laminated magnetic inductor. A second magnetic stack is formed opposite a surface of the first magnetic stack in an outer region of the laminated magnetic inductor. A third magnetic stack is formed opposite a surface of the second magnetic stack in a second inner region of the laminated magnetic inductor. The insulating layers are formed such that a thickness of an insulating layer in the second magnetic stack is greater than a thickness of an insulating layer in the first magnetic stack.

Abstract: A method for planarizing a metal conductor layer embedded in a dielectric layer is provided. The method includes removing a portion of an overburden of the metal conductor layer that is formed over the dielectric layer with a first CMP slurry. The method also includes removing a remaining portion of the overburden of the metal conductor layer with a second CMP slurry to expose upper portions of the dielectric layer.

Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer.

Abstract: Embodiments of the invention are directed to a method of fabricating a yoke arrangement of an inductor. A non-limiting example method includes forming a dielectric layer across from a major surface of a substrate. The method further includes configuring the dielectric layer such that it imparts a predetermined dielectric layer compressive stress on the substrate. A magnetic stack is formed on an opposite side of the dielectric layer from the substrate, wherein the magnetic stack includes one or more magnetic layers alternating with one or more insulating layers. The method further includes configuring the magnetic stack such that it imparts a predetermined magnetic stack tensile stress on the dielectric layer, wherein a net effect of the predetermined dielectric layer compressive stress and the predetermined magnetic stack tensile stress on the substrate is insufficient to cause a portion of the major surface of the substrate to be substantially non-planar.

Abstract: Embodiments are directed to a method of forming a laminated magnetic inductor and resulting structures having multiple magnetic layer thicknesses. A first magnetic stack having one or more magnetic layers alternating with one or more insulating layers is formed in a first inner region of the laminated magnetic inductor. A second magnetic stack is formed opposite a major surface of the first magnetic stack in an outer region of the laminated magnetic inductor. A third magnetic stack is formed opposite a major surface of the second magnetic stack in a second inner region of the laminated magnetic inductor. The magnetic layers are formed such that a thickness of a magnetic layer in each of the first and third magnetic stacks is less than a thickness of a magnetic layer in the second magnetic stack.

Abstract: A method of forming a microfluidic device is disclosed. The method includes forming a first dielectric layer on a substrate, forming electrodes partially into the first dielectric layer, and forming a second dielectric layer on the electrodes. The method includes filling, with a metal material, two wells formed in the second dielectric layer such that the metal material is in direct contact with the electrodes. The method includes forming a third dielectric layer on the metal material and second dielectric layer. The method includes filling, with a structural material, a channel formed between the wells such that the structural material does not directly contact the electrodes. The method includes forming a fourth dielectric layer on the third dielectric layer and the structural material, extracting the structural material through at least one vent hole in the fourth dielectric layer, and forming a fifth dielectric layer on the fourth dielectric layer.

Abstract: Embodiments of the invention include a method of using a sensor. The method includes accessing a sample and exposing the sample to the sensor. The sensor includes a sensing circuit having with a field effect transistor (FET) having a gate structure. A cavity is formed in a fill material that is over the gate structure. A probe of the sensor is within a portion of the cavity. An upper region of the probe is above a top surface of the fill material, and a lower region of the probe is below the top surface of the fill material. The probe structure includes a 3D sensing surface structure, and a liner is formed on the 3D sensing surface and configured to function as a recognition element. A portion of the liner is on the lower region of the probe and positioned between sidewalls of the cavity and the 3D sensing surface.

Abstract: Embodiments of the invention are directed to a sensor that includes a sensing circuit and a probe communicatively coupled to the sensing circuit. The probe includes a three-dimensional (3D) sensing surface coated with a recognition element and configured to, based at least in part on the 3D sensing surface interacting with a predetermined material, generate a first measurement. In some embodiments, the 3D sensing surface is shaped as a pyramid, a cone, or a cylinder to increase the sensing surface area over a two-dimensional (2D) sensing surface. In some embodiments, the 3D sensing surface facilitates penetration of the 3D sensing surface through the wall of the biological cell.

Abstract: Embodiments are directed to a method of forming a laminated magnetic inductor and resulting structures having anisotropic magnetic layers. A first magnetic stack is formed having one or more magnetic layers alternating with one or more insulating layers. A trench is formed in the first magnetic stack oriented such that an axis of the trench is perpendicular to a hard axis of the magnetic inductor. The trench is filled with a dielectric material.

Abstract: A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space.

Abstract: A method for fabricating a magnetic material stack on a substrate, comprises forming a first dielectric layer, forming a first magnetic material layer on the first dielectric layer, forming at least a second dielectric layer on the first magnetic material layer and forming at least a second magnetic material layer on the second dielectric layer. During one or more of the forming steps, a surface smoothing operation is performed to remove at least a portion of surface roughness on the layer being formed.

Abstract: A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space.

Abstract: Embodiments of the invention are directed to a method of fabricating a yoke arrangement of an inductor. A non-limiting example method includes forming a dielectric layer across from a major surface of a substrate. The method further includes configuring the dielectric layer such that it imparts a predetermined dielectric layer compressive stress on the substrate. A magnetic stack is formed on an opposite side of the dielectric layer from the substrate, wherein the magnetic stack includes one or more magnetic layers alternating with one or more insulating layers. The method further includes configuring the magnetic stack such that it imparts a predetermined magnetic stack tensile stress on the dielectric layer, wherein a net effect of the predetermined dielectric layer compressive stress and the predetermined magnetic stack tensile stress on the substrate is insufficient to cause a portion of the major surface of the substrate to be substantially non-planar.

Abstract: An on-chip magnetic structure includes a palladium activated seed layer and a substantially amorphous magnetic material disposed onto the palladium activated seed layer. The substantially amorphous magnetic material includes nickel in a range from about 50 to about 80 atomic % (at. %) based on the total number of atoms of the magnetic material, iron in a range from about 10 to about 50 at. % based on the total number of atoms of the magnetic material, and phosphorous in a range from about 0.1 to about 30 at. % based on the total number of atoms of the magnetic material. The magnetic material can include boron in a range from about 0.1 to about 5 at. % based on the total number of atoms of the magnetic material.

Abstract: A spin-transfer torque magneto-resistive random access memory (STT-MRAM) device is provided. The STT-MRAM device includes a substrate, a dielectric layer and a magnetic tunnel junction (MTJ) stack. The substrate includes a conductor and a landing pad. The MTJ stack includes a reference layer element, a free layer assembly and a barrier layer element. The reference layer element is lined with redeposited metal and is disposed on the landing pad within the dielectric layer. The free layer assembly includes a free layer element, a hard mask layer element disposed on the free layer element, redeposited metal lining sidewalls of the free and hard mask layer elements and dielectric material lining the redeposited metal. The barrier layer element is interposed between and has a same width as the reference layer element and the free layer assembly.

Abstract: Embodiments of the invention are directed to a sensor that includes a sensing circuit and a probe communicatively coupled to the sensing circuit. The probe includes a three-dimensional (3D) sensing surface coated with a recognition element and configured to, based at least in part on the 3D sensing surface interacting with a predetermined material, generate a first measurement. In some embodiments, the 3D sensing surface is shaped as a pyramid, a cone, or a cylinder to increase the sensing surface area over a two-dimensional (2D) sensing surface. In some embodiments, the 3D sensing surface facilitates penetration of the 3D sensing surface through the wall of the biological cell.

Abstract: A first material is filled during a semiconductor fabrication process in a space bound on at least one side by a fence formation created as a result of an etching operation. A solvent-removable material is deposited such that the solvent-removable material encapsulates at least that portion of the fence formation which is protruding from the structure such that a height of the fence formation exceeds a height of the structure. The portion of the fence formation which is protruding from the structure and a first portion of the solvent-removable material are removed by planarization. A second portion of the solvent-removable material is removed by dissolving in a solvent, the second portion remaining after removal by the planarization of the first portion of the solvent-removable material.

Abstract: A method for forming an inductor device. The method comprises forming a trench within a central core region of a conductive coil formed within a dielectric material. The method further comprises forming a composite region within the trench. The composite region including a polymer matrix having a plurality of particles with magnetic properties dispersed therein with the central core region to reduce eddy current loss and increase energy storage.

Abstract: An on-chip magnetic structure includes a magnetic material comprising cobalt in a range from about 80 to about 90 atomic % (at. %) based on the total number of atoms of the magnetic material, tungsten in a range from about 4 to about 9 at. % based on the total number of atoms of the magnetic material, phosphorous in a range from about 7 to about 15 at. % based on the total number of atoms of the magnetic material, and palladium substantially dispersed throughout the magnetic material.

Abstract: A magnetic material stack comprises a first dielectric layer, a first magnetic material layer on the first dielectric layer, at least a second dielectric layer on the first magnetic material layer and at least a second magnetic material layer on the second dielectric layer. One or more surfaces of the layers are smoothed to remove at least a portion of surface roughness on the respective layers.