Patents by Inventor Eugene J. O'Sullivan

Eugene J. O'Sullivan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BIOSENSOR ELECTRODE HAVING THREE-DIMENSIONAL STRUCTURED SENSING SURFACES
    Publication number: 20180275093
    Abstract: Embodiments of the invention are directed to a sensor that includes a sensing circuit and a probe communicatively coupled to the sensing circuit. The probe includes a three-dimensional (3D) sensing surface coated with a recognition element and configured to, based at least in part on the 3D sensing surface interacting with a predetermined material, generate a first measurement. In some embodiments, the 3D sensing surface is shaped as a pyramid, a cone, or a cylinder to increase the sensing surface area over a two-dimensional (2D) sensing surface. In some embodiments, the 3D sensing surface facilitates penetration of the 3D sensing surface through the wall of the biological cell.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 27, 2018
    Inventors: Bruce B. Doris, Eugene J. O'Sullivan, Sufi Zafar
  • FORMING SELF-ALIGNED CONTACTS ON PILLAR STRUCTURES
    Publication number: 20180261649
    Abstract: A method of forming a semiconductor structure includes forming two or more pillar structures over a top surface of a substrate. The method also includes forming two or more contacts to the two or more pillar structures. The method further includes forming an insulator between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 13, 2018
    Inventors: Anthony J. Annunziata, Daniel C. Edelstein, Eugene J. O'Sullivan, Henry K. Utomo
  • SELECTIVE GROWTH OF SEED LAYER FOR MAGNETO-RESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20180261763
    Abstract: A method of fabricating a magneto-resistive random access memory (MRAM) cell with at least one magnetic tunnel junction (MTJ) is provided. The method includes disposing a metallic landing pad within a dielectric pad in a substrate and selectively depositing seed layer material over the substrate. This selective deposition forms a seed layer on which the MTJ is disposable on the metallic landing pad but not the dielectric pad.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 13, 2018
    Inventors: ANTHONY J. ANNUNZIATA, CHANDRASEKHARAN KOTHANDARAMAN, NATHAN P. MARCHACK, EUGENE J. O'SULLIVAN
  • COMBINED CMP AND RIE CONTACT SCHEME FOR MRAM APPLICATIONS
    Publication number: 20180254411
    Abstract: A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.
    Type: Application
    Filed: April 24, 2018
    Publication date: September 6, 2018
    Inventors: Michael F. Lofaro, Nathan P. Marchack, Janusz J. Nowak, Eugene J. O'Sullivan
  • COMBINED CMP AND RIE CONTACT SCHEME FOR MRAM APPLICATIONS
    Publication number: 20180254410
    Abstract: A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.
    Type: Application
    Filed: November 1, 2017
    Publication date: September 6, 2018
    Inventors: Michael F. Lofaro, Nathan P. Marchack, Janusz J. Nowak, Eugene J. O'Sullivan
  • METHOD OF FORMING AN ON-PITCH SELF-ALIGNED HARD MASK FOR CONTACT TO A TUNNEL JUNCTION USING ION BEAM ETCHING
    Publication number: 20180240967
    Abstract: A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.
    Type: Application
    Filed: April 18, 2018
    Publication date: August 23, 2018
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CROCUS TECHNOLOGY
    Inventors: Michael C. Gaidis, Erwan Gapihan, Rohit Kilaru, Eugene J. O'Sullivan
  • Patterning magnetic films using self-stop electro-etching
    Patent number: 10049802
    Abstract: A semiconductor structure includes a substrate and a patterned magnetic feature disposed over a top surface of the substrate. The patterned magnetic feature is a magnetic material, and has undercut sidewalls providing a self-stop for electro-etching of the magnetic material. The semiconductor structure may form a closed-yoke inductor or a solenoid inductor.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Eugene J. O'Sullivan, David L. Rath, Naigang Wang
  • INDUCTORS IN BEOL WITH PARTICULATE MAGNETIC CORES
    Publication number: 20180218823
    Abstract: An inductor device includes a conductive coil formed within a dielectric material and having a central core area within the coil. Particles are dispersed within the central core region to reduce eddy current loss and increase energy storage. The particles include magnetic properties.
    Type: Application
    Filed: January 30, 2017
    Publication date: August 2, 2018
    Inventors: Chandrasekharan Kothandaraman, Eugene J. O'Sullivan, Naigang Wang
  • INDUCTORS IN BEOL WITH PARTICULATE MAGNETIC CORES
    Publication number: 20180218824
    Abstract: An inductor device includes a conductive coil formed within a dielectric material and having a central core area within the coil. Particles are dispersed within the central core region to reduce eddy current loss and increase energy storage. The particles include magnetic properties.
    Type: Application
    Filed: November 2, 2017
    Publication date: August 2, 2018
    Inventors: Chandrasekharan Kothandaraman, Eugene J. O'Sullivan, Naigang Wang
  • MAGNETIC INDUCTOR STACKS
    Publication number: 20180197670
    Abstract: A magnetic laminating inductor structure and process for preventing substrate bowing and damping losses generally include a laminated film stack including a magnetic layer having a tensile stress, an insulating layer having a compressive stress disposed on the magnetic layer, and a dielectric planarizing layer on the insulating layer. The dielectric planarizing layer has a neutral stress and a roughness value less than the insulating layer. The reduction in surface roughness reduces damping losses and the compressive stress of the insulating layers reduces wafer bowing.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 12, 2018
    Inventors: HARIKLIA DELIGIANNI, BRUCE B. DORIS, EUGENE J. O'SULLIVAN, NAIGANG WANG
  • MAGNETIC INDUCTOR STACKS
    Publication number: 20180197671
    Abstract: A magnetic laminating inductor structure and process for preventing substrate bowing and damping losses generally include a laminated film stack including a magnetic layer having a tensile stress, an insulating layer having a compressive stress disposed on the magnetic layer, and a dielectric planarizing layer on the insulating layer. The dielectric planarizing layer has a neutral stress and a roughness value less than the insulating layer. The reduction in surface roughness reduces damping losses and the compressive stress of the insulating layers reduces wafer bowing.
    Type: Application
    Filed: November 1, 2017
    Publication date: July 12, 2018
    Inventors: HARIKLIA DELIGIANNI, BRUCE B. DORIS, EUGENE J. O'SULLIVAN, NAIGANG WANG
  • STRUCTURE AND METHOD TO REDUCE SHORTING AND PROCESS DEGRADATION IN STT-MRAM DEVICES
    Publication number: 20180190900
    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.
    Type: Application
    Filed: February 27, 2018
    Publication date: July 5, 2018
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
  • STRUCTURE AND METHOD TO REDUCE SHORTING AND PROCESS DEGRADATION IN STT-MRAM DEVICES
    Publication number: 20180190901
    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.
    Type: Application
    Filed: February 27, 2018
    Publication date: July 5, 2018
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
  • Combined CMP and RIE contact scheme for MRAM applications
    Patent number: 10014464
    Abstract: A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael F. Lofaro, Nathan P. Marchack, Janusz J. Nowak, Eugene J. O'Sullivan
  • High resistivity iron-based, thermally stable magnetic material for on-chip integrated inductors
    Patent number: 10002919
    Abstract: An on-chip magnetic structure includes a palladium activated seed layer and a substantially amorphous magnetic material disposed onto the palladium activated seed layer. The substantially amorphous magnetic material includes nickel in a range from about 50 to about 80 atomic % (at. %) based on the total number of atoms of the magnetic material, iron in a range from about 10 to about 50 at. % based on the total number of atoms of the magnetic material, and phosphorous in a range from about 0.1 to about 30 at. % based on the total number of atoms of the magnetic material. The magnetic material can include boron in a range from about 0.1 to about 5 at. % based on the total number of atoms of the magnetic material.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 19, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, William J. Gallagher, Maurice Mason, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang
  • Method of forming an on-pitch self-aligned hard mask for contact to a tunnel junction using ion beam etching
    Patent number: 10003014
    Abstract: A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: June 19, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, CROCUS TECHNOLOGY
    Inventors: Michael C. Gaidis, Erwan Gapihan, Rohit Kilaru, Eugene J. O'Sullivan
  • Structure and method to reduce shorting and process degradation in STT-MRAM devices
    Patent number: 9960347
    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: May 1, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
  • PATTERNING MAGNETIC FILMS USING SELF-STOP ELECTRO-ETCHING
    Publication number: 20180102207
    Abstract: A semiconductor structure includes a substrate and a patterned magnetic feature disposed over a top surface of the substrate. The patterned magnetic feature is a magnetic material, and has undercut sidewalls providing a self-stop for electro-etching of the magnetic material. The semiconductor structure may form a closed-yoke inductor or a solenoid inductor.
    Type: Application
    Filed: May 5, 2017
    Publication date: April 12, 2018
    Inventors: Eugene J. O'Sullivan, David L. Rath, Naigang Wang
  • MAGNETIC MATERIAL STACK AND MAGNETIC INDUCTOR STRUCTURE FABRICATED WITH SURFACE ROUGHNESS CONTROL
    Publication number: 20180096771
    Abstract: A method for fabricating a magnetic material stack on a substrate includes the following steps. A first dielectric layer is formed. A first magnetic material layer is formed on the first dielectric layer. At least a second dielectric layer is formed on the first magnetic material layer. At least a second magnetic material layer is formed on the second dielectric layer. During one or more of the forming steps, a surface smoothing operation is performed to remove at least a portion of surface roughness on the layer being formed. The magnetic material stack can be used to form a low magnetic loss yoke inductor.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Magnetic multilayer structure
    Patent number: 9929209
    Abstract: A mechanism is provided for an integrated laminated magnetic device. A substrate and a multilayer stack structure form the device. The multilayer stack structure includes alternating magnetic layers and diode structures formed on the substrate. Each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by a diode structure.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: March 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Philipp Herget, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang, Bucknell C. Webb