Patents by Inventor Eui Hong

Eui Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100273226
    Abstract: Provided herein is an isolated polynucleotide for increasing the alcohol tolerance of a host cell. Also disclosed herein are a vector and a host cell containing the isolated polynucleotide, and a method of increasing the volumetric productivity of a bioalcohol using the same.
    Type: Application
    Filed: September 11, 2009
    Publication date: October 28, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung Jo YU, Jae Chan PARK, Sung Min PARK, Dae Hyeok KWEON, Min Eui HONG
  • Publication number: 20100270558
    Abstract: Provided are a method of fabricating a polycrystalline silicon thin film using high temperature heat generated by Joule heating induced by application of an electrical field to a conductive layer, which can ensure process stability at high temperature and thus processing time can be reduced and a polycrystalline silicon thin film having excellent crystallinity can be obtained, a polycrystalline thin film using the method and a thin film transistor including the polycrystalline thin film.
    Type: Application
    Filed: November 21, 2008
    Publication date: October 28, 2010
    Applicant: ENSILTECH CORPORATION
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Publication number: 20100244038
    Abstract: Provided are thin film transistor, a method of fabricating the same, a flat panel display device including the same, and a method of fabricating the flat panel display device, that are capable of applying an electric field to a gate line to form a channel region of a semiconductor layer of a thin film transistor using a polysilicon layer crystallized by a high temperature heat generated by Joule heating of a conductive layer. As a result, a process can be simplified using a gate line included in the thin film transistor as the conductive layer, and the channel region of the semiconductor layer can be formed of polysilicon having a uniform degree of crystallinity. The thin film transistor includes a straight gate line disposed in one direction, a semiconductor layer crossing the gate line, and source and drain electrodes connected to source and drain regions of the semiconductor layer.
    Type: Application
    Filed: November 20, 2008
    Publication date: September 30, 2010
    Applicant: ENSILTECH CORPORATION
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Publication number: 20100233858
    Abstract: Disclosed herein is a rapid annealing method in a mixed structure composed of a heat treatment-requiring material, dielectric layer and conductive layer, comprising that during rapid annealing on a predetermined part of the heat treatment-requiring material, by instantaneously generated intense heat due to Joule heating by application of an electric field to the conductive layer, the potential difference between the heat treatment-requiring material and the conductive layer is set lower than the dielectric break-down voltage of the dielectric layer, thereby preventing generation of arc by dielectric breakdown of the dielectric layer during the annealing.
    Type: Application
    Filed: January 10, 2007
    Publication date: September 16, 2010
    Applicants: ENSILTECH CORPORATION
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Publication number: 20100223215
    Abstract: Systems and methods for making demographic predictions for websites and web-pages. Embodiments include a system and a method of making demographic predictions for websites. The system and method select one or more websites with known demographic attributes for use as training websites, obtain demographic attributes data of the training websites, determine first features of web-pages of the training websites and develop a prediction model using the determined first features and the obtained demographic attributes data. The prediction model predicts one or more values for a target demographic attribute. The system and method determine second features of web-pages of a target website and apply the prediction model to the determined second features of the target website to predict one or more values for the target demographic attribute of the target website.
    Type: Application
    Filed: December 21, 2009
    Publication date: September 2, 2010
    Applicant: nXn Tech, LLC
    Inventors: George Karypis, Eui-Hong Han
  • Publication number: 20100161385
    Abstract: Systems and methods for predicting characteristics of a web user, determining a combination of websites to obtain a target demographic mix, determining a set of keywords to buy to obtain a target demographic mix, selecting websites from market research and designing websites to appeal to an audience with desired demographic characteristics. Systems and methods may include determining features of web-pages of ad-carrying, target websites, applying prediction models to the determined features of the ad-carrying, target websites to predict values of demographic attributes of the ad-carrying, target websites, receiving one or more inputs including a target demographic mix, receiving a number that indicates an amount of visitors of the ad-carrying, target websites, and determining a combination of websites that provide target demographic mix based on the predicted values of the demographic attributes and number of visitors of the ad-carrying, target websites.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 24, 2010
    Applicant: nXn Tech, LLC
    Inventors: George Karypis, Eui-Hong Han
  • Patent number: 7713827
    Abstract: Disclosed herein is a method of making a semiconductor device. According to the method, a flowable oxide (FOX) is deposited over a semiconductor substrate, and a local active region is exposed to grow an active region, by a silicon epitaxial growth (SEG) method, to prevent generation of a void when a device isolation structure is formed by a Shallow Trench Isolation (STI) method, and to prevent formation of stress between the semiconductor substrate and the FOX.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: May 11, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yeong Eui Hong
  • Patent number: 7679105
    Abstract: Provided are a hetero-junction bipolar transistor (HBT) that can increase data processing speed and a method of manufacturing the hetero-junction bipolar transistor.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: March 16, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong Won Kim, Eun Soo Nam, Ho Young Kim, Sang Seok Lee, Dong Suk Jun, Hong Yeol Lee, Seon Eui Hong, Dong Young Kim, Jong Won Lim, Myoung Sook Oh
  • Patent number: 7638856
    Abstract: Provided are an optoelectronic (OE) transmitter integrated circuit (IC) and method of fabricating the same using a selective growth process. In the OE transmitter IC, a driving circuit, which includes a double heterojunction bipolar transistor (DHBT) and amplifies received electric signals to drive an electroabsorption (EA) modulator, and the EA modulator with a multi-quantum well (MQW) absorption layer are integrated as a single chip on a semi-insulating substrate. The MQW absorption layer of the EA modulator and an MQW insertion layer of the DHBT are formed to different thicknesses from each other using a selective MOCVD growth process.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: December 29, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eun Soo Nam, Yong Won Kim, Seon Eui Hong, Myung Sook Oh, Bo Woo Kim
  • Publication number: 20090239328
    Abstract: A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region.
    Type: Application
    Filed: April 23, 2009
    Publication date: September 24, 2009
    Inventors: Eun Soo Nam, Seon Eui Hong, Myoung Sook Oh, Yong Won Kim, Ho Young Kim, Bo Woo Kim
  • Publication number: 20090140291
    Abstract: A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region.
    Type: Application
    Filed: December 7, 2006
    Publication date: June 4, 2009
    Inventors: Eun Soo Nam, Seon Eui Hong, Myoung Sook Oh, Yong Won Kim, Ho Young Kim, Bo Woo Kim
  • Patent number: 7541659
    Abstract: A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolated the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: June 2, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eun Soo Nam, Seon Eui Hong, Myoung Sook Oh, Yong Won Kim, Ho Young Kim, Bo Woo Kim
  • Publication number: 20090107091
    Abstract: Provided is a byproduct collecting apparatus for efficiently collecting reaction-byproducts contained in an exhaust gas exhausted from a process chamber during a semiconductor manufacturing process. The apparatus includes a housing and a trap module. The housing has a gas inlet port and a gas outlet port. The trap module is installed inside the housing and has first plates curved or inclined to guide an exhaust gas flow in a curved fashion.
    Type: Application
    Filed: April 25, 2007
    Publication date: April 30, 2009
    Inventors: Che-Hoo Cho, Jung-Eui Hong, Tae-Woo Kim, In-Mun Hwang
  • Publication number: 20090042342
    Abstract: The present invention provides a method for preparation of crystallization of amorphous silicon thin film, which comprises providing a forming a amorphous silicon on a dielectric film formed on a transparent substrate; then forming a conductive layer on the top surface of substrate; applying an electric field to the conductive layer so as to generate heat; and crystallization of amorphous silicon thin film by the generated heat.
    Type: Application
    Filed: March 5, 2007
    Publication date: February 12, 2009
    Applicant: ENSILTECH CO., LTD.
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Publication number: 20090004815
    Abstract: Disclosed herein is a method of making a semiconductor device. According to the method, a flowable oxide (FOX) is deposited over a semiconductor substrate, and a local active region is exposed to grow an active region, by a silicon epitaxial growth (SEG) method, to prevent generation of a void when a device isolation structure is formed by a Shallow Trench Isolation (STI) method, and to prevent formation of stress between the semiconductor substrate and the FOX.
    Type: Application
    Filed: November 5, 2007
    Publication date: January 1, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Yeong Eui Hong
  • Patent number: D584265
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: January 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gi-Young Lee, Hyun-Seop Kim, Kwan-Eui Hong, Chang-Soo Lee
  • Patent number: D584273
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: January 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwan-Eui Hong, Hyun-Seop Kim, Chang-Soo Lee
  • Patent number: D593518
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: June 2, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwan-Eui Hong, Hyun-Seop Kim, Chang-Soo Lee
  • Patent number: D593519
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: June 2, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwan-Eui Hong, Hyun-Seop Kim, Chang-Soo Lee
  • Patent number: D599316
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: September 1, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwan-Eui Hong, Hyun-Seop Kim, Chang-Soo Lee