Abstract: The present disclosure provides storage devices and methods for operating the same. In some embodiments, a storage device includes a non-volatile memory including a plurality of sub-blocks that are independently erasable, and a processor configured to control a garbage collection operation on the plurality of sub-blocks. The plurality of sub-blocks includes a plurality of first sub-blocks that have a first block size and a plurality of second sub-blocks that have a second block size. The second block size is different from the first block size. The processor is further configured to select a victim sub-block with a lowest ratio of a valid page count to an invalid page count from among the plurality of sub-blocks, and copy a valid page of the victim sub-block to a target sub-block from among the plurality of sub-blocks.

Abstract: A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.

Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

Abstract: A storage device includes a nonvolatile memory device and a storage controller to control operation of the nonvolatile memory device. The storage controller assigns a program operation associated with data to be programmed, to one of a first program operation or a second program operation, controls the nonvolatile memory device to perform the first program operation on first memory blocks and to perform the second program operation on at least one second memory block, and controls the nonvolatile memory to select one of the first program operation on a third memory block in an erase state or the second program operation on the second memory block, and to perform the selected program operation after the first program operation on the first memory blocks is completed.

Abstract: A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of word-lines, a plurality of memory cells provided in a plurality of channel holes and a word-line cut region extending in a first horizontal direction and dividing the word-lines into a plurality of memory blocks. A plurality of target memory cells coupled to each of the plurality of word-lines are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells. The control circuit controls a program operation on target memory cells coupled to a target word-line of the plurality of word-lines such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits. The second number is a natural number greater than the first number.

Abstract: A storage device includes a non-volatile memory device. The non-volatile memory device includes a first substrate including a first peripheral circuit region including a row decoder selecting one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array and a second substrate including a second peripheral circuit region, including a page buffer unit selecting at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region. The 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.

Abstract: A method of operating a memory system that comprises a memory device including a plurality of memory blocks and a memory controller, includes detecting a first memory block having a degradation count greater than or equal to a first reference value by the memory controller. A first command for the first memory block is transmitted to the memory device by the memory controller. A first voltage is applied to all of a plurality of word lines connected to the first memory block and a second voltage to a bit line connected to the first memory block in response to the first command by the memory device. The first voltage is greater than a voltage applied to turn on memory cells connected to all of the plurality of word lines. The second voltage is greater than a voltage applied to the bit line during program, read or erase operations.

Abstract: A method of operating a memory system includes programming, in a memory device, K logical pages stored in a page buffer circuit into a memory cell array, reading, from the memory device, the K logical pages programmed into the memory cell array into the page buffer circuit after a first delay time elapses, transmitting, in a memory controller, N?K logical pages to the memory device, and programming, in the memory device, N logical pages into the memory cell array based on the read K logical pages and the N?K logical pages, wherein K is a positive integer and N is a positive integer greater than K.

Abstract: A non-volatile memory device includes a substrate, a stack structure that includes a first gate layer that extends in a horizontal direction and a second gate layer that extends in the horizontal direction and is disposed apart from the first gate layer in a vertical direction, a plurality of first channel structures that penetrate in the vertical direction through a first channel region of the stack structure, a plurality of second channel structures that penetrate in the vertical direction through a second channel region of the stack structure, a first anti-fuse structure and a second anti-fuse structure that each penetrate in the vertical direction through an anti-fuse region of the stack structure, a first anti-fuse transistor that is electrically connected to the first gate layer through the first anti-fuse structure, and a second anti-fuse transistor that is electrically connected to the second gate layer through the second anti-fuse structure.

Abstract: A storage device, including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array including a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes, and a word-line cut region dividing the plurality of word-lines into a plurality of memory blocks. The storage controller groups a plurality of target memory cells into outer cells and inner cells. The storage controller includes an error correction code (ECC) decoder configured to perform an ECC decoding operation by obtaining outer cell bits and inner cell bits during a read operation on the plurality of target memory cells, and applying different log likelihood ratio (LLR) values to the outer cell bits and the inner cell bits.

Abstract: A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.

Abstract: A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.

Abstract: A storage device includes a NAND flash memory device, an auxiliary memory device and a storage controller to control the NAND flash memory device and the auxiliary memory device. The storage controller includes a processor, an error correction code (ECC) engine and a memory interface. The processor executes a flash translation layer (FTL) loaded onto an on-chip memory. The ECC engine generates first parity bits for user data to be stored in a target page of the NAND flash memory device based on error attribute of a target memory region associated with the target page, and selectively generates additional parity bits for the user data under control of the processor. The memory interface transmits the user data and the first parity bits to the NAND flash memory device, and selectively transmits the additional parity bits to the auxiliary memory device.

Abstract: Provided is a three-dimensional storage device using wafer-to-wafer bonding. A storage device includes a first chip including a first substrate and a peripheral circuit region including a first control logic circuit configured to control operation modes of the non-volatile memory device and a second chip including a second substrate and three-dimensional arrays of non-volatile memory cells. The second chip may be vertically stacked on the first chip so that a first surface of the first substrate faces a first surface of the second substrate, and a second control logic circuit is configured to control operation conditions of the non-volatile memory device and is arranged on a second surface of the second substrate, the second surface of the second substrate being opposite to the first surface of the second substrate of the second chip.

Abstract: Provided is a semiconductor device. The semiconductor device includes: a plurality of insulating layers and a plurality of gate electrodes alternately arranged in a first direction; and a plurality of channel structures passing through the plurality of gate electrodes and the plurality of insulating layers in the first direction, wherein each of the plurality of gate electrodes includes: a first conductive layer including an inner wall surrounding the plurality of channel structures; and a second conductive layer that is separated from the plurality of channel structures in a second direction perpendicular to the first direction, wherein resistivity of the second conductive layer is less than resistivity of the first conductive layer.

Abstract: A nonvolatile memory (NVM) device includes a plurality of memory blocks and a control logic receiving a specific command and an address. The control logic may perform a cell count-based dynamic read (CDR) operation on memory cells connected to one of wordlines of a selected block, among the plurality of memory blocks, in response to the address. The control logic includes a cell count comparator circuit configured to compare: (1) a first cell count value for a highest state among a plurality of states with at least one reference value according to the CDR operation and (2) a second cell count value for an erase state among the plurality of states with the at least one reference value. Additionally, the control logic includes a read level selector configured to select a read level according to a result of the comparison of the cell count comparator circuit.

Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

Abstract: A memory system for performing a recovery operation is provided. A memory system includes a memory device including a plurality of memory cells constituting a plurality of sub-sets, and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating a number of read operations performed by the memory device for each of the plurality of sub-sets, and to perform a recovery operation on a sub-set, among the plurality of sub-sets, based on the read count corresponding to the read count. Each of a plurality of sub-sets includes a plurality of pages. Each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells.

Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.