Patents by Inventor Eun Chu Oh

Eun Chu Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10566066
    Abstract: A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Jeong So, Dong-Hwan Lee, Seong-Hyeog Choi, Eun-Chu Oh, Jun-Jin Kong, Hong-Rak Son, Pil-Sang Yoon
  • Patent number: 10559362
    Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Jin Shin, Ji Su Kim, Dae Seok Byeon, Ji Sang Lee, Jun Jin Kong, Eun Chu Oh
  • Publication number: 20190377632
    Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.
    Type: Application
    Filed: March 20, 2019
    Publication date: December 12, 2019
    Inventors: Eun-chu Oh, Moo-sung Kim, Young-sik Kim, Yong-jun Lee, Jeong-ho Lee
  • Publication number: 20190369921
    Abstract: A storage device includes a nonvolatile memory including a plurality of nonvolatile memory cells, a write buffer memory storing first data and second data received from a host, and a storage controller storing the first data and the second data that are stored in the write buffer memory into the nonvolatile memory. The storage controller performs a first program operation and a second program operation on a plurality of first memory cells connected to a first word line group to store the first data, and performs a first program operation and a second program operation on a plurality of second memory cells connected to a second word line group to store the second data. While the storage controller performs the first program operation on the plurality of second memory cells, the first data is written in the write buffer memory.
    Type: Application
    Filed: May 24, 2019
    Publication date: December 5, 2019
    Inventors: Eun Chu OH, Younggeun LEE, Youngjin CHO, Jin-Hyeok CHOI
  • Publication number: 20190362794
    Abstract: An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.
    Type: Application
    Filed: August 13, 2019
    Publication date: November 28, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Eun Chu OH, Pilsang Yoon, Jun Jin Kong, Jisu Kim, Hong Rak Son, Jinbae Bang, Daeseok Byeon, Taehyun Song, Dongjin Shin, Dongsup Jin
  • Patent number: 10467133
    Abstract: A storage device is provided as follows. A nonvolatile memory device includes blocks, each block having sub-blocks erased independently. A memory controller performs a garbage collection operation on the nonvolatile memory device by selecting a garbage collection victim sub-block among the sub-blocks and erasing the selected garbage collection victim sub-block to generate a free sub-block. The memory controller selects the garbage collection victim sub-block using valid page information of each sub-block and valid page information of memory cells adjacent to each sub-block.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Amitai Perlstein, Eun Chu Oh, Amir Bennatan, Junjin Kong, Hong Rak Son
  • Publication number: 20190279731
    Abstract: A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Inventors: HYE-JEONG SO, DONG-HWAN LEE, SEONG-HYEOG CHOI, EUN-CHU OH, JUN-JIN KONG, HONG-RAK SON, PIL-SANG YOON
  • Publication number: 20190252027
    Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.
    Type: Application
    Filed: September 25, 2018
    Publication date: August 15, 2019
    Inventors: Dong Jin Shin, Ji Su Kim, Dae Seok Byeon, Ji Sang Lee, Jun Jin Kong, Eun Chu Oh
  • Patent number: 10381090
    Abstract: An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: August 13, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Chu Oh, Pilsang Yoon, Jun Jin Kong, Jisu Kim, Hong Rak Son, Jinbae Bang, Daeseok Byeon, Taehyun Song, Dongjin Shin, Dongsup Jin
  • Patent number: 10332606
    Abstract: A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Jeong So, Dong-Hwan Lee, Seong-Hyeog Choi, Eun-Chu Oh, Jun-Jin Kong, Hong-Rak Son, Pil-Sang Yoon
  • Patent number: 10229749
    Abstract: A nonvolatile memory storage system includes a plurality of memory cells and a memory controller configured to transmit a read command to a nonvolatile memory device based on a plurality of read voltages. The nonvolatile memory device performs a first read operation on a first level among the N levels based on a first read voltage among the plurality of read voltages, counts the number of on-cells that respond to the first read voltage among the plurality of memory cells, and adjusts a level of a second read voltage to be used to perform a second read operation on the first level or a second level among the N levels among the plurality of read voltages according to a comparison result of the counted number of on-cells and the number of reference cells.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Chu Oh, Pilsang Yoon, Jun Jin Kong, Hong Rak Son, Dongsup Jin
  • Publication number: 20190051353
    Abstract: A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.
    Type: Application
    Filed: October 16, 2018
    Publication date: February 14, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Eun-chu OH, Pil-sang Yoon, Jun-jin Kong, Hong-rak Son
  • Publication number: 20180358101
    Abstract: A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.
    Type: Application
    Filed: March 14, 2018
    Publication date: December 13, 2018
    Inventors: HYE-JEONG SO, DONG-HWAN LEE, SEONG-HYEOG CHOI, EUN-CHU OH, JUN-JIN KONG, HONG-RAK SON, PIL-SANG YOON
  • Patent number: 10127978
    Abstract: A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-chu Oh, Pil-sang Yoon, Jun-jin Kong, Hong-rak Son
  • Patent number: 10121543
    Abstract: A storage device includes a nonvolatile memory device including a plurality of memory cells, the memory cells divided into a plurality of pages, and a controller configured to control the nonvolatile memory device. The storage device is configured to collect two or more write data groups to be written to two or more pages, to simultaneously perform a common write operation with the two or more pages based on the two or more write data groups, and to sequentially perform an individual write operation with each of the two or more pages based on the two or more write data groups.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: November 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Chu Oh, Jun Jin Kong, Hong Rak Son, Pilsang Yoon
  • Publication number: 20180294036
    Abstract: An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.
    Type: Application
    Filed: June 8, 2018
    Publication date: October 11, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Eun Chu OH, Pilsang YOON, Jun Jin KONG, Jisu KIM, Hong Rak SON, Jinbae BANG, Daeseok BYEON, Taehyun SONG, Dongjin SHIN, Dongsup JIN
  • Publication number: 20180286495
    Abstract: A nonvolatile memory storage system includes a plurality of memory cells and a memory controller configured to transmit a read command to a nonvolatile memory device based on a plurality of read voltages. The nonvolatile memory device performs a first read operation on a first level among the N levels based on a first read voltage among the plurality of read voltages, counts the number of on-cells that respond to the first read voltage among the plurality of memory cells, and adjusts a level of a second read voltage to be used to perform a second read operation on the first level or a second level among the N levels among the plurality of read voltages according to a comparison result of the counted number of on-cells and the number of reference cells.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Eun Chu OH, Pilsang YOON, Jun Jin KONG, Hong Rak SON, Dongsup JIN
  • Patent number: 10007572
    Abstract: A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Min Shin, Jun-Jin Kong, Beom-Kyu Shin, Eun-Chu Oh, Pil-Sang Yoon
  • Patent number: 9952766
    Abstract: A memory device capable of performing an overwrite operation, a memory system, and a method of operating the memory system are provided. The method includes receiving one or more write requests, a logical address and data corresponding to the one or more write requests; comparing a result of analyzing at least one of the received one or more write requests, logical address, and data with a threshold value; and writing data using a first update method or a second update method, based on a result of the comparison. When the first update method is selected, the data are written in a region indicated by a physical address corresponding to the logical address according to address mapping information. When the second update method is selected, information of the physical address corresponding to the logical address is changed, and the data are written in a region indicated by the changed physical address.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jae Woo, Kyoung-Il Bang, Sung-Yong Seo, Eun-Chu Oh, Moon-Sang Kwon, Han-Shin Shin
  • Patent number: 9881671
    Abstract: A method is for operating a resistive memory system including a resistive memory device implemented as multi-level memory cells. The method includes setting levels of reference voltages used to determine resistance states of the multi-level memory cells, and reading data of the multi-level memory cells based on the reference voltages. A difference between the reference voltages used to determine a relatively high resistance state is greater than a difference between the reference voltages used to determine a relatively low resistance state.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: January 30, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Chu Oh, Young-Geon Yoo, Jun Jin Kong, Hong-Rak Son, Han-Shin Shin