Abstract: One aspect of the present disclosure is a pharmaceutical composition which includes (R)—N-[1-(3,5-difluoro-4-methansulfonylamino-phenyl)-ethyl]-3-(2-propyl-6-trifluoromethyl-pyridin-3-yl)-acrylamide as a first component and a cellulosic polymer as a second component, wherein the composition of one aspect of the present disclosure has a formulation characteristic in which crystal formation is delayed for a long time.

Abstract: The present invention relates to a composition for forming a composite polymer film, a method for preparing the composition for forming a composite polymer film, a composite polymer film and a method for preparing the composite polymer film. The composition for forming a composite polymer film comprises: a fluorine-based polymer solution comprising a fluorine-based polymer; and polyvinylidene fluoride nanoparticles dispersed in the fluorine-based polymer solution. The method for preparing the composition for forming a composite polymer film comprises the steps of: preparing a fluorine-based polymer solution comprising a fluorine-based polymer; and dispersing polyvinylidene fluoride nanoparticles in the fluorine-based polymer solution. The composite polymer film comprises: a polymer matrix formed from a fluorine-based polymer; and polyvinylidene fluoride nanoparticles dispersed in the polymer matrix.

Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: Type-switching transistors, electronic devices including the same, and methods of operating thereof are provided. A type-switching transistor may include a plurality of gates corresponding to a channel layer. The plurality of gates may include a first gate for switching a type of the transistor and a second gate for controlling ON/OFF characteristics of the channel layer. The first and second gates may be disposed on one side of the channel layer so that the channel layer is not disposed between the first and second gates.

Abstract: A semiconductor device according to example embodiments may include a channel including a nanowire and a charge storage layer including nanoparticles. A twin gate structure including a first gate and a second gate may be formed on the charge storage layer. The semiconductor device may be a memory device or a diode.

Abstract: A static random access memory (SRAM) includes: a first carbon nanotube (CNT) inverter, a second CNT inverter, a first switching transistor, and a second switching transistor. The first CNT inverter includes at least a first CNT transistor. The second CNT inverter is connected to the first CNT inverter and includes at least one second CNT transistor. The first switching transistor is connected to the first CNT inverter. The second switching transistor is connected to the second CNT inverter.

Abstract: A non-volatile memory device including a variable resistance material is provided. The non-volatile memory device may include a buffer layer, a variable resistance material layer and/or an upper electrode, for example, sequentially formed on a lower electrode. A schottky barrier may be formed on an interface between the buffer layer and the lower electrode. The variable resistance material layer may be formed with a variable resistance property.

Abstract: A non-volatile variable resistance memory device and a method of fabricating the same are provided. The non-volatile variable resistance memory device may include a lower electrode, a buffer layer on the lower electrode, an oxide layer on the buffer layer and an upper electrode on the oxide layer. The buffer layer may be composed of an oxide and the oxide layer may have variable resistance characteristics.

Abstract: Provided is a method of forming a metal oxide film on a CNT and a method of fabricating a carbon nanotube transistor using the same. The method includes forming chemical functional group on a surface of the CNT and forming the metal oxide film on the CNT on which the chemical functional group is formed.

Abstract: Provided is a method of manufacturing carbon nanotube (CNT) device arrays. In the method of manufacturing CNT device arrays, catalyst patterns may be formed using a photolithography process, CNTs may be grown from the catalyst patterns, and electrodes may be formed on the grown CNTs.

Abstract: A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.

Abstract: Type-switching transistors, electronic devices including the same, and methods of operating thereof are provided. A type-switching transistor may include a plurality of gates corresponding to a channel layer. The plurality of gates may include a first gate for switching a type of the transistor and a second gate for controlling ON/OFF characteristics of the channel layer. The first and second gates may be disposed on one side of the channel layer so that the channel layer is not disposed between the first and second gates.

Abstract: A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer.

Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

Abstract: A non-volatile memory device includes a first oxide layer, a second oxide layer and a buffer layer formed on a lower electrode. An upper electrode is formed on the buffer layer. In one example, the lower electrode is composed of at least one of Pt, Ru, Ir, IrOx and an alloy thereof, the second oxide layer is a transition metal oxide, the buffer layer is composed of a p-type oxide and the upper electrode is composed of a material selected from Ni, Co, Cr, W, Cu or an alloy thereof.

Abstract: A nonvolatile memory device includes at least one switching device and at least one storage node electrically connected to the at least one switching device. The at least one storage node includes a lower electrode, one or more oxygen-deficient metal oxide layers, one or more data storage layers, and an upper electrode. At least one of the one or more metal oxide layers is electrically connected to the lower electrode. At least one of the one or more data storage layers is electrically connected to at least one of the one or more metal oxide layers. The upper electrode is electrically connected to at least one of the one or more data storage layers. A method of manufacturing the nonvolatile memory device includes preparing the at least one switching device and forming the lower electrode, one or more metal oxide layers, one or more data storage layers, and upper electrode.

Abstract: A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube between the source electrode and the drain electrode, a gate insulating layer formed on the carbon nanotubes, and a gate electrode formed on the gate insulating layer.

Abstract: Provided is a method of transferring carbon nanotubes formed on a donor substrate to an acceptor substrate which may include vertically forming carbon nanotubes on a first substrate, providing a second substrate, aligning the first substrate with the second substrate so that the carbon nanotubes face the second substrate, and transferring the carbon nanotubes onto the second substrate by pressing the first substrate onto the second substrate.

Abstract: A semiconductor device according to example embodiments may include a channel including a nanowire and a charge storage layer including nanoparticles. A twin gate structure including a first gate and a second gate may be formed on the charge storage layer. The semiconductor device may be a memory device or a diode.

Abstract: A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer.