Abstract: Provided are a resistance random access memory including a resistance layer having a metal oxide and/or a metal ion dopant, which may be deposited at room temperature and which may have variable resistance characteristics, and a method of manufacturing the same.

Abstract: A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.

Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

Abstract: A non-volatile memory device including a variable resistance material is provided. The non-volatile memory device may include a buffer layer, a variable resistance material layer and/or an upper electrode, for example, sequentially formed on a lower electrode. A schottky barrier may be formed on an interface between the buffer layer and the lower electrode. The variable resistance material layer may be formed with a variable resistance property.

Abstract: Example embodiments are directed to a junction field effect thin film transistor (JFETFT) including a first electrode formed on a substrate, a first conductive first gate semiconductor pattern formed on the first gate electrode, a second conductive semiconductor channel layer formed on the substrate and the first conductive first gate semiconductor pattern, and source and drain electrodes formed on the second conductive semiconductor pattern and located at both sides of the first conductive gate semiconductor pattern. The JFETFT may further include a first conductive second gate semiconductor pattern formed on a portion of the second conductive semiconductor channel layer between the source electrode and the drain electrode, and a second gate electrode formed on the first conductive second gate semiconductor pattern.

Abstract: Provided is a variable resistance random access memory device having an n+ interfacial layer and a method of fabricating the same. The variable resistance random access memory device may include a lower electrode, an n+ interfacial layer on the lower electrode, a buffer layer on the n+ interfacial layer, an oxide layer on the buffer layer and having a variable resistance characteristic and an upper electrode on the oxide layer.

Abstract: A non-volatile variable resistance memory device and a method of fabricating the same are provided. The non-volatile variable resistance memory device may include a lower electrode, a buffer layer on the lower electrode, an oxide layer on the buffer layer and an upper electrode on the oxide layer. The buffer layer may be composed of an oxide and the oxide layer may have variable resistance characteristics.

Abstract: A nonvolatile memory device includes at least one switching device and at least one storage node electrically connected to the at least one switching device. The at least one storage node includes a lower electrode, one or more oxygen-deficient metal oxide layers, one or more data storage layers, and an upper electrode. At least one of the one or more metal oxide layers is electrically connected to the lower electrode. At least one of the one or more data storage layers is electrically connected to at least one of the one or more metal oxide layers. The upper electrode is electrically connected to at least one of the one or more data storage layers. A method of manufacturing the nonvolatile memory device includes preparing the at least one switching device and forming the lower electrode, one or more metal oxide layers, one or more data storage layers, and upper electrode.

Abstract: A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.

Abstract: A non-volatile memory device comprises a first oxide layer, a second oxide layer and a buffer layer formed on a lower electrode. An upper electrode is formed on the buffer layer. In one example, the lower electrode is composed of at least one of Pt, Ru, Ir, IrOx and an alloy thereof, the second oxide layer is a transition metal oxide, the buffer layer is composed of a p-type oxide and the upper electrode is composed of a material selected from Ni, Co, Cr, W, Cu or an alloy thereof.

Abstract: A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer.

Abstract: An electrode structure having at least two oxide layers that more reliably switch and operate without the use of additional devices and a non-volatile memory device having the same are provided. The electrode structure may include a lower electrode, a first oxide layer formed on the lower electrode, a second oxide layer formed on the first oxide layer and an upper electrode formed on the second oxide layer wherein at least one of the first and second oxide layers may be formed of a resistance-varying material. The first oxide layer may be formed of an oxide having a variable oxidation state.

Abstract: Provided are a storage node, a nonvolatile memory device, methods of fabricating the same and a method of operating the nonvolatile memory device. The storage node may include a lower metal layer and a first insulation layer, an intermediate metal layer, a second insulation layer, an upper metal layer and a nano layer, which are sequentially stacked on the lower metal layer. The nonvolatile memory device may include a switching device and the storage node connected to the switching device.

Abstract: A programming method for a phase-change random access memory (PRAM) may be provided. The programming method may include determining an amorphous state of a chalcogenide material using programming pulses to form programming areas having threshold voltages corresponding to logic high and logic low, and/or controlling a trailing edge of programming pulses during programming to control a quenching speed of the chalcogenide material so as to adjust a threshold voltage of the chalcogenide material. Accordingly, programming pulses corresponding to logic low or logic high may have uniform magnitudes regardless of a corresponding logic level. Accordingly, reliability of a PRAM device may be improved.

Abstract: Resistive memory devices having at least one varistor and methods of operating the same are disclosed. The resistive memory device may include at least one bottom electrode line, at least one top electrode line crossing the at least one bottom electrode line, and at least one stack structure disposed at an intersection of the at least one top electrode line and the at least one bottom electrode line including a varistor and a data storage layer.

Abstract: Provided are a surface electron emission device and a display device having the same. The surface electron emission device may include a lower electrode, an insulating layer, and an upper electrode sequentially stacked, and a nano structure layer formed on the upper electrode.

Abstract: A storage node having a metal-insulator-metal structure, a non-volatile memory device including a storage node having a metal-insulator-metal (MIM) structure and a method of operating the same are provided. The memory device may include a switching element and a storage node connected to the switching element. The storage node may include a first metal layer, a first insulating layer and a second metal layer, sequentially stacked, and a nano-structure layer. The storage node may further include a second insulating layer and a third metal layer. The nano-structure layer, which is used as a carbon nano-structure layer, may include at least one fullerene layer.

Abstract: Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured to store information in a first manner, a first diode having a first end connected to the source of the transistor, the first diode configured to rectify a flow of current from the source of the transistor and a second storage node connected to a second end of the first diode, the second storage node configured to store information in a second manner.

Abstract: In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device, and a lower stack structure formed under the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device.

Abstract: A non-volatile memory device with improved integration and/or improved performance by reducing an area per bit and controlling a body bias, and a method of fabricating the same. The non-volatile memory device may use surface portions of the outer side surfaces and/or the upper surfaces of at least one pair of fins protruding from a body and extending, spaced from each other along one direction, as at least one pair of channel regions. At least one control gate electrode may be formed across the channel regions, and at least one pair of storage nodes may be interposed in at least one portion between the control gate electrode and the channel regions.