Patents by Inventor Eun Jeong Kim

Eun Jeong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200022888
    Abstract: The present invention relates to a capsule comprising a pigment and a method for producing the same. More specifically, the present invention relates to a capsule which comprises therein a pigment inside which is likely to be discolored due to external environment, and thereby can easily crack or break and cause color development when applied to the skin, while isolating the pigment from the external environment, and a method for producing the same.
    Type: Application
    Filed: September 26, 2017
    Publication date: January 23, 2020
    Applicant: AMOREPACIFIC CORPORATION
    Inventors: Yan LI, Hyun Suk LEE, Sun Kyung CHOI, Yong Jin KIM, John Hwan LEE, Eun Jeong KIM
  • Publication number: 20190284053
    Abstract: Provided a high-pressure homogenizer comprising a channel module comprising a microchannel through which an object for homogenization passes, wherein the microchannel is provided with a first flow channel and a second flow channel sequentially arranged along the direction through which the object passes, the first flow channel is provided with a plurality of first baffles disposed so as to partition the microchannel into a plurality of spaces, the second flow channel is provided with a plurality of second baffles disposed so as to partition the microchannel into a plurality of spaces, and at least one of the first baffles is provided to be positioned between two adjacent second baffles.
    Type: Application
    Filed: October 13, 2017
    Publication date: September 19, 2019
    Applicant: LG Chem, Ltd.
    Inventors: Eun Jeong Kim, Kwang Hyun Yoo, Ye Hoon Im, In Young Kim, Won Jong Kwon
  • Patent number: 10395973
    Abstract: A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventors: Eun-Jeong Kim, Jin-Yul Lee, Han-Sang Song, Su-Ho Kim
  • Publication number: 20190189501
    Abstract: A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
    Type: Application
    Filed: February 15, 2019
    Publication date: June 20, 2019
    Inventors: Eun-Jeong KIM, Jin-Yul LEE, Han-Sang SONG, Su-Ho KIM
  • Patent number: 10256136
    Abstract: A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: April 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Eun-Jeong Kim, Jin-Yul Lee, Han-Sang Song, Su-Ho Kim
  • Patent number: 10239654
    Abstract: A packing box includes first and second sidewall parts spaced apart and facing each other, first and second connecting parts, a third connecting part attaching the second connecting part to the first sidewall part, a bottom part connecting lower portions of the first and second sidewall parts and the first and second connecting parts, and a top part facing the bottom part and connecting upper portions of the first and second sidewall parts and the first and second connecting parts to form a receiving space. The top part includes first to fourth upper paperboards folded and extended from the upper portions of the first and second sidewall parts and the first and second connecting parts to form a handle, and a fifth upper paperboard folded from the third connecting part and disposed under the first to fourth upper paperboards to prevent withdrawal of contents from the receiving space.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 26, 2019
    Assignee: YUHA PRINTING & PACKAGING CO., LTD.
    Inventors: Jae Hyun Choi, Beak Jin Kim, Ji Hun Jeong, Eun Jeong Kim
  • Publication number: 20180214888
    Abstract: The present invention relates to an apparatus for exfoliating a plate-shaped material for exfoliating graphene, which has features that while a shear force required for the exfoliation of graphite is applied using a specific microchannel, it can simultaneously prevent the graphene itself from being crushed and increase the discharge flow rate of a graphene dispersion, thereby enhancing the production efficiency of graphene.
    Type: Application
    Filed: September 23, 2016
    Publication date: August 2, 2018
    Applicant: LG Chem, Ltd.
    Inventors: Kwang Hyun Yoo, Eun Jeong Kim, In Young Kim, Ye Hoon Im, Won Jong Kwon
  • Publication number: 20180215622
    Abstract: The present invention relates to a peeling device of sheet material for peeling off graphite, and the peeling device of sheet material according to the present invention is characterized in that a specific microchannel is used to apply a shear force required to peel off graphite, and simultaneously, graphene itself is not ground and the discharge flow rate of the graphene dispersion increases to increase graphene preparation efficiency.
    Type: Application
    Filed: September 23, 2016
    Publication date: August 2, 2018
    Applicant: LG Chem, Ltd.
    Inventors: Kwang Hyun Yoo, Eun Jeong Kim, In Young Kim, Pum Suk Park, Ye Hoon Im, Won Jong Kwon
  • Publication number: 20180141022
    Abstract: The present invention relates to a peeling device of sheet material for peeling off graphite, and the peeling device of sheet material according to the present invention is characterized in that a specific microchannel is used to apply a shear force required to peel off graphite, and simultaneously, various sizes of shear forces can be applied according to the sections in the microchannel, thus increasing graphene preparation efficiency.
    Type: Application
    Filed: September 7, 2016
    Publication date: May 24, 2018
    Applicant: LG Chem, Ltd.
    Inventors: Eun Jeong Kim, Kwang Hyun Yoo, Ye Hoon Im, In Young Kim, Won Jong Kwon
  • Publication number: 20180090368
    Abstract: A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Eun-Jeong KIM, Jin-Yul Lee, Han-Sang Song, Su-Ho Kim
  • Patent number: 9865496
    Abstract: A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: January 9, 2018
    Assignee: SK Hynix Inc.
    Inventors: Eun-Jeong Kim, Jin-Yul Lee, Han-Sang Song, Su-Ho Kim
  • Patent number: 9786598
    Abstract: A semiconductor device includes: a first plug; a bit line which is in contact with the first plug and over the first plug and extended in one direction; a second plug including a first part adjacent to the bit line and a second part adjacent to the first plug; a double air gap which is disposed between the first part of the second plug and the bit line and includes a first air gap surrounding the first part of the second plug and a second air gap parallel to sidewalls of the bit line; and a capping layer suitable for capping the first and second air gaps.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 10, 2017
    Assignee: SK Hynix Inc.
    Inventors: Eun-Jeong Kim, Jin-Yul Lee
  • Publication number: 20170186844
    Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.
    Type: Application
    Filed: July 12, 2016
    Publication date: June 29, 2017
    Inventors: Dong-Soo KIM, Sung-Won LIM, Eun-Jeong KIM, Hyun-Jin CHANG, Keun HEO, Jee-Hyun KIM
  • Publication number: 20170186642
    Abstract: A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
    Type: Application
    Filed: August 12, 2016
    Publication date: June 29, 2017
    Inventors: Eun-Jeong KIM, Jin-Yul LEE, Han-Sang SONG, Su-Ho KIM
  • Publication number: 20170183119
    Abstract: A packing box includes first and second sidewall parts spaced apart and facing each other, first and second connecting parts, a third connecting part attaching the second connecting part to the first sidewall part, a bottom part connecting lower portions of the first and second sidewall parts and the first and second connecting parts, and a top part facing the bottom part and connecting upper portions of the first and second sidewall parts and the first and second connecting parts to form a receiving space. The top part includes first to fourth upper paperboards folded and extended from the upper portions of the first and second sidewall parts and the first and second connecting parts to form a handle, and a fifth upper paperboard folded from the third connecting part and disposed under the first to fourth upper paperboards to prevent withdrawal of contents from the receiving space.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 29, 2017
    Applicant: YUHA PRINTING & PACKAGING CO., LTD.
    Inventors: Jae Hyun CHOI, Beak Jin KIM, Ji Hun JEONG, Eun Jeong KIM
  • Patent number: 9634109
    Abstract: A semiconductor device including a substrate in which a trench is formed, a first impurity region and a second impurity region formed in the substrate separated from each other by the trench, a gate electrode formed to fill a lower part of the trench, and a capping layer formed over the gate electrode to fill an upper part of the trench. The gate electrode includes a first work function liner formed over a bottom surface and sidewalls of the lower part of the trench without overlapping with the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed over the sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: April 25, 2017
    Assignee: SK Hynix Inc.
    Inventors: Tae-Kyung Oh, Jin-Yul Lee, Eun-Jeong Kim, Dong-Soo Kim
  • Publication number: 20170047421
    Abstract: A semiconductor device including a substrate in which a trench is formed, a first impurity region and a second impurity region formed in the substrate separated from each other by the trench, a gate electrode formed to fill a lower part of the trench, and a capping layer formed over the gate electrode to fill an upper part of the trench. The gate electrode includes a first work function liner formed over a bottom surface and sidewalls of the lower part of the trench without overlapping with the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed over the sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Tae-Kyung OH, Jin-Yul LEE, Eun-Jeong KIM, Dong-Soo KIM
  • Patent number: 9508847
    Abstract: A semiconductor device including a substrate in which a trench is formed, a first impurity region and a second impurity region formed in the substrate separated from each other by the trench, a gate electrode formed to fill a lower part of the trench, and a capping layer formed over the gate electrode to fill an upper part of the trench. The gate electrode includes a first work function liner formed over a bottom surface and sidewalls of the lower part of the trench without overlapping with the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed over the sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: November 29, 2016
    Assignee: SK Hynix Inc.
    Inventors: Tae-Kyung Oh, Jin-Yul Lee, Eun-Jeong Kim, Dong-Soo Kim
  • Patent number: 9469544
    Abstract: The present invention relates to a method for manufacturing polysilicon. According to the present invention, meltdown can be prevented during the growth of silicon rod, and a polycrystalline silicon rod having a larger diameter can be shortly manufactured with a minimal consumption of energy.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: October 18, 2016
    Assignee: HANWHA CHEMICAL CORPORATION
    Inventors: Hyun-Cheol Ryu, Jea Sung Park, Dong-Ho Lee, Eun-Jeong Kim, Gui Ryong Ahn, Sung Eun Park
  • Patent number: 9451226
    Abstract: The present disclosure relates to a white balance method for performing a shading compensation, and more particularly, a white balance method for performing a shading compensation, in which a white balance control is initiated for an input image captured when a camera is driven, and then the shading compensation is performed together during a process of performing the initiated white balance control. The white balance method for performing a shading compensation includes executing a white balance for adjusting a color temperature of an input image, extracting a shading gain table corresponding to the color temperature among pre-stored shading gain tables for each color temperature during the execution of the white balance, executing a shading compensation for an image for each block of the input image by using the extracted shading gain table, and terminating the white balance.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: September 20, 2016
    Assignee: Hanwha Techwin Co., Ltd.
    Inventors: Young Je Jung, Eun Jeong Kim