Patents by Inventor Eun KO

Eun KO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11257801
    Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang-Eun Lee, Hyung-Dong Lee, Eun Ko
  • Patent number: 10792371
    Abstract: Provided is a conjugate including a c-Met targeting compound and a bioactive material and methods of use of the conjugate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Young Chae, Sunghyun Kim, Eun Ko, Yun Ju Jeong, Jae Hyun Choi
  • Publication number: 20190355707
    Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.
    Type: Application
    Filed: August 1, 2019
    Publication date: November 21, 2019
    Applicant: SK hynix Inc.
    Inventors: Sang-Eun LEE, Hyung-Dong LEE, Eun KO
  • Patent number: 10418353
    Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang-Eun Lee, Hyung-Dong Lee, Eun Ko
  • Publication number: 20180331087
    Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.
    Type: Application
    Filed: September 26, 2017
    Publication date: November 15, 2018
    Applicant: SK hynix Inc.
    Inventors: Sang-Eun LEE, Hyung-Dong LEE, Eun KO
  • Publication number: 20180236097
    Abstract: Provided is a conjugate including a c-Met targeting compound and a bioactive material and methods of use of the conjugate.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 23, 2018
    Inventors: Su Young Chae, Sunghyun Kim, Eun Ko, Yun Ju Jeong, Jae Hyun Choi
  • Patent number: 10002850
    Abstract: A semiconductor chip may include a semiconductor substrate having a front surface and a rear surface which faces away from the front surface. The semiconductor chip may include a fixed metal layer formed over the front surface of the semiconductor substrate, and having first metal lines formed in the fixed metal layer. The semiconductor chip may include a configurable metal layer formed over the fixed metal layer to have one surface which faces the fixed metal layer and the other surface which faces away from the one surface, and having second metal lines formed in the configurable metal layer such that at least one end of the second metal lines disposed on the one surface are respectively connected with the first metal lines and other ends of the second metal lines facing away from the at least one end are disposed at predetermined positions on the other surface.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: June 19, 2018
    Assignee: SK hynix Inc.
    Inventors: Sang Eun Lee, Eun Ko, Yong Jae Park
  • Patent number: 9966359
    Abstract: A semiconductor package may be provided. The semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip flip-chip bonded to a first surface of the substrate. The semiconductor package may include second semiconductor chips respectively flip-chip bonded to portions of the first surface of the substrate adjacent to both ends of the first semiconductor chip. The semiconductor package may include a third semiconductor chip solder-jointed to the first surface of the substrate covering the first semiconductor chip and portions of the second semiconductor chips.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 8, 2018
    Assignee: SK hynix Inc.
    Inventors: Sang Eun Lee, Eun Ko, Yong Jae Park
  • Patent number: 9889206
    Abstract: Disclosed is a conjugate in which a c-Met targeting compound and a bioactive material are chemically conjugated with each other, and methods of use thereof.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Young Chae, Sunghyun Kim, Eun Ko, Yun Ju Jeong, Jae Hyun Choi
  • Publication number: 20170317056
    Abstract: The present disclosure provides a semiconductor chip including a semiconductor substrate having a front surface and a rear surface which faces away from the front surface. The semiconductor chip includes a fixed metal layer formed over the front surface of the semiconductor substrate, and having first metal lines formed in the fixed metal layer. The semiconductor chip includes a configurable metal layer formed over the fixed metal layer to have one surface which faces the fixed metal layer and the other surface which faces away from the one surface, and having second metal lines formed in the configurable metal layer such that at least one end of the second metal lines disposed on the one surface are respectively connected with the first metal lines and other ends of the second metal lines facing away from the at least one end are disposed at predetermined positions on the other surface.
    Type: Application
    Filed: July 28, 2016
    Publication date: November 2, 2017
    Inventors: Sang Eun LEE, Eun KO, Yong Jae PARK
  • Patent number: 9780071
    Abstract: A semiconductor package may include a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface. The semiconductor package may include one or more reconfigurable package units each including a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch on a second active surface; a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch; a molding layer surrounding side surfaces of the second semiconductor chip and the semiconductor chip connector; and redistribution lines formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: October 3, 2017
    Assignee: SK hynix Inc.
    Inventors: Sang Eun Lee, Eun Ko, Yong Jae Park
  • Patent number: 9711482
    Abstract: A semiconductor package may include first semiconductor chips disposed in a rotationally symmetrical structure. First bonding pads are arranged over the bottom surfaces of the first semiconductor chips. The semiconductor package may also include a first encapsulation member formed to surround at least side surfaces of the first semiconductor chips. The semiconductor package may also include via patterns formed in the first encapsulation member. The semiconductor package may also include second semiconductor chips stacked over top surfaces of the first semiconductor chips and the first encapsulation member including the via patterns in such a way as to form step shapes with the first semiconductor chips. Second bonding pads electrically connected to the via patterns are arranged over bottom surfaces of the second semiconductor chips.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: July 18, 2017
    Assignee: SK hynix Inc.
    Inventors: Sang Eun Lee, Eun Ko, Yong Jae Park
  • Patent number: 9607667
    Abstract: A memory device includes a plurality of channels that respectively include memory cell arrays and local input/output lines electrically coupled to the memory cell arrays and are independently operable, shared global input/output lines electrically coupled to the local input/output lines included in the plurality of channels and having a connection relation controlled through one or more path switch circuits arranged among the plurality of channels, and the path switch circuits that control the connection relation of the shared global input/output lines according to a path control signal.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: March 28, 2017
    Assignee: SK HYNIX INC.
    Inventors: Sang Eun Lee, Eun Ko
  • Publication number: 20170084575
    Abstract: A semiconductor package may be provided. The semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip flip-chip bonded to a first surface of the substrate. The semiconductor package may include second semiconductor chips respectively flip-chip bonded to portions of the first surface of the substrate adjacent to both ends of the first semiconductor chip. The semiconductor package may include a third semiconductor chip solder-jointed to the first surface of the substrate covering the first semiconductor chip and portions of the second semiconductor chips.
    Type: Application
    Filed: December 15, 2015
    Publication date: March 23, 2017
    Inventors: Sang Eun LEE, Eun KO, Yong Jae PARK
  • Publication number: 20170076762
    Abstract: A memory device includes a plurality of channels that respectively include memory cell arrays and local input/output lines electrically coupled to the memory cell arrays and are independently operable, shared global input/output lines electrically coupled to the local input/output lines included in the plurality of channels and having a connection relation controlled through one or more path switch circuits arranged among the plurality of channels, and the path switch circuits that control the connection relation of the shared global input/output lines according to a path control signal.
    Type: Application
    Filed: February 25, 2016
    Publication date: March 16, 2017
    Inventors: Sang Eun LEE, Eun KO
  • Publication number: 20170062384
    Abstract: A semiconductor package may include first semiconductor chips disposed in a rotationally symmetrical structure. First bonding pads are arranged over the bottom surfaces of the first semiconductor chips. The semiconductor package may also include a first encapsulation member formed to surround at least side surfaces of the first semiconductor chips. The semiconductor package may also include via patterns formed in the first encapsulation member. The semiconductor package may also include second semiconductor chips stacked over top surfaces of the first semiconductor chips and the first encapsulation member including the via patterns in such a way as to form step shapes with the first semiconductor chips. Second bonding pads electrically connected to the via patterns are arranged over bottom surfaces of the second semiconductor chips.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 2, 2017
    Inventors: Sang Eun LEE, Eun KO, Yong Jae PARK
  • Publication number: 20170018527
    Abstract: A semiconductor package may include a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface. The semiconductor package may include one or more reconfigurable package units each including a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch on a second active surface; a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch; a molding layer surrounding side surfaces of the second semiconductor chip and the semiconductor chip connector; and redistribution lines formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer.
    Type: Application
    Filed: October 16, 2015
    Publication date: January 19, 2017
    Inventors: Sang Eun LEE, Eun KO, Yong Jae PARK
  • Publication number: 20150071950
    Abstract: Disclosed is a conjugate in which a c-Met targeting compound and a bioactive material are chemically conjugated with each other, and methods of use thereof.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 12, 2015
    Inventors: Su Young Chae, Sunghyun Kim, Eun Ko, Yun Ju Jeong, Jae Hyun Choi
  • Publication number: 20140106394
    Abstract: Provided is a multiwell plate for an easy liquid removal, wherein the mutiwell plate includes a well with at least one pore in the sidewall defining the well, and a method of analyzing a target material using the multiwell plate.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 17, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Eun KO, Moon-sook Lee
  • Publication number: 20140080211
    Abstract: Provided is a multiwell plate that includes first wells and second wells separated by a sidewall made of a porous material and a method of using the same.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 20, 2014
    Inventors: Moon-sook LEE, Eun KO, Min-sang KIM