Abstract: A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation, a read and write circuit suitable for applying an initial setting voltage, to bit lines of at least one memory block during the erase operation, and a control logic suitable for controlling the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the erase voltage to the source line.

Abstract: A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.

Abstract: A pharmaceutical composition for preventing or treating muscle atrophy or sarcopenia including glucagon-like peptide-1 (GLP-1), a GLP-1 fragment, a GLP-1 secretion enhancer, a GLP-1 degradation inhibitor, a GLP-1 receptor (GLP-1R) agonist, or exendin-4, and a method of treating muscle atrophy or sarcopenia by using the pharmaceutical composition. When the pharmaceutical composition is administered to a subject having sarcopenia or muscle atrophy, reduced body weight, skeletal muscle mass, and grip strength, which are caused by sarcopenia or muscle atrophy, and expression levels of genes involved in muscle production may be restored to normal states. The composition may be widely applied to the development of effective therapeutic agents for sarcopenia or muscle atrophy.

Abstract: An organic light-emitting display device and a method of fabricating the same are provided. The organic light-emitting display device includes a substrate having a plurality of trenches; a thin film transistor on the substrate; a light-emitting diode connected to the thin film transistor; an upper auxiliary electrode connected to one of an anode and a cathode of the light-emitting diode; and a lower auxiliary electrode in an auxiliary electrode trench among the plurality of trenches of the substrate and connected to the upper auxiliary electrode.

Abstract: Provided are a porous metal halide film that reacts with an organic halide to be converted into an organometal halide having a perovskite structure, thereby fabricating the organometal halide, a fabrication method thereof, and a fabrication method of an organometal halide having a perovskite structure using the same, and specifically, the porous metal halide film according to the present disclosure satisfies Relational Expression 1 below: I(101)/I(001)?0.5??(Relational Expression 1) in Relational Expression 1, I(101) is a diffraction intensity of a (101) plane in X-ray diffraction pattern using a Cu K? line of the porous metal halide film, and I(001) is a diffraction intensity of the (001) plane in the same X-ray diffraction pattern.

Abstract: A washing machine in which a first main heater is not driven while wash water stored in a first tub and wash water stored in a second tub are simultaneously heated, and a method of controlling the same. A washing machine includes: a first tub configured to store wash water; a first main heater configured to heat wash water stored in the first tub; a first sub heater configured to heat wash water stored in the first tub; a second tub configured to store wash water; and a second heater configured to heat wash water stored in the second tub, wherein a power consumption required to drive the first main heater is greater than a power consumption required to drive the first sub heater, and the first main heater is not driven while wash water stored in the first tube and wash water stored in the second tub are simultaneously heated.

Abstract: An organic light-emitting display device and a method of fabricating the same are provided. The organic light-emitting display device includes a substrate having a plurality of trenches; a thin film transistor on the substrate; a light-emitting diode connected to the thin film transistor; an upper auxiliary electrode connected to one of an anode and a cathode of the light-emitting diode; and a lower auxiliary electrode in an auxiliary electrode trench among the plurality of trenches of the substrate and connected to the upper auxiliary electrode.

Abstract: A washing machine and a method for controlling the same are disclosed. The washing machine includes a plurality of washing devices, each of which includes a heater. Based on a target temperature of wash water heated by one heater of any one of the washing devices, the washing machine changes a target temperature setting environment of wash water heated by the remaining heater. The washing machine includes a first heater to heat wash water stored in a first tub, a second heater to heat wash water stored in a second tub, a control panel to provide a target temperature setting menu for setting a target temperature of the wash water stored in the first tub, and a controller to drive the first heater and the second heater. The controller changes the target temperature setting menu supplied from the control panel in response to the second target temperature.

Abstract: Provided are a pharmaceutical composition for preventing or treating muscle atrophy or sarcopenia including glucagon-like peptide-1 (GLP-1), a GLP-1 fragment, a GLP-1 secretion enhancer, a GLP-1 degradation inhibitor, a GLP-1 receptor (GLP-1R) agonist, or exendin-4, and a method of treating muscle atrophy or sarcopenia by using the pharmaceutical composition. When the pharmaceutical composition for preventing or treating muscle atrophy or sarcopenia provided in the present invention is administered to a subject having sarcopenia or muscle atrophy, reduced body weight, skeletal muscle mass, and grip strength, which are caused by sarcopenia or muscle atrophy, and expression levels of genes involved in muscle production may be restored to normal states, and therefore, the composition may be widely applied to the development of effective therapeutic agents for sarcopenia or muscle atrophy.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation, a read and write circuit suitable for applying an initial setting voltage, to bit lines of at least one memory block during the erase operation, and a control logic suitable for controlling the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the erase voltage to the source line.

Abstract: Disclosed is an organic light emitting display having a mirror function. In an embodiment, a light-shielding reflective layer overlaps areas of the organic light emitting display except for emission areas provided with light emitting devices formed therein. The light-shielding reflective layer prevents light from entering channel regions of active layers and reflects external light, for example, when the organic light emitting device is not operated to display an image, and thus the organic light emitting display may stably implement a mirror function.

Abstract: A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.

Abstract: There are provided a memory system having improved reliability and an operating method thereof. A memory system includes a semiconductor memory device including a memory cell array having a plurality of pages, and a controller for sequentially transmitting, to the semiconductor memory device, physical block addresses of pages to be programmed among the plurality of pages. In the memory system, the semiconductor memory device selects a page corresponding to each of the physical block addresses among the plurality of pages according to previously stored program speed information, and performs a program operation on the selected page.

Abstract: A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.

Abstract: A method of inhibiting the growth of cancer stem cells, including administering an effective amount of a protein kinase D1 expression or activity inhibitor as an active ingredient to a subject having cancer is provided. Further, a method of treating cancer, including administering an effective amount of a protein kinase D1 expression or activity inhibitor, and antitumor agent as active ingredients to a subject having cancer is provided. Further, a method for measuring expression or activity of protein kinase D1 for providing information of breast cancer prognosis, including a step of measuring expression or activity of protein kinase D1 in cells or tissues isolated from a subject is provided.

Abstract: Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array, peripheral circuits, and a control logic. The memory cell array may include a plurality of memory strings. The peripheral circuits may program the memory cell array. The control logic may control the peripheral circuits and execute instructions for performing a first program operation by applying a program voltage to at least two selected word lines, among a plurality of word lines of the memory cell array, at a same time, and, after the first program operation, performing a second program operation by applying the program voltage to each of the selected word lines one at a time.

Abstract: Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include: drain select transistor coupled to a bit line; a source select transistor coupled to a source line; a plurality of memory cells coupled in series between the drain select transistor and the source select transistor; and a peripheral circuit configured to successively apply a discharge control voltage to memory cells in sequence from a memory cell adjacent to the source select transistor to a memory cell adjacent to the drain select transistor.

Abstract: Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include: drain select transistor coupled to a bit line; a source select transistor coupled to a source line; a plurality of memory cells coupled in series between the drain select transistor and the source select transistor; and a peripheral circuit configured to successively apply a discharge control voltage to memory cells in sequence from a memory cell adjacent to the source select transistor to a memory cell adjacent to the drain select transistor.

Abstract: An organic light-emitting display device and a method of fabricating the same are provided. The organic light-emitting display device includes a substrate having a plurality of trenches; a thin film transistor on the substrate; a light-emitting diode connected to the thin film transistor; an upper auxiliary electrode connected to one of an anode and a cathode of the light-emitting diode; and a lower auxiliary electrode in an auxiliary electrode trench among the plurality of trenches of the substrate and connected to the upper auxiliary electrode.