Patents by Inventor Eun-Chul Ahn
Eun-Chul Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9685400Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: GrantFiled: January 29, 2016Date of Patent: June 20, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
-
Patent number: 9484292Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: GrantFiled: April 28, 2014Date of Patent: November 1, 2016Assignee: SAMSUNG ELECTRONICS CO. LTD.Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
-
Patent number: 9449918Abstract: A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width.Type: GrantFiled: July 14, 2015Date of Patent: September 20, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon-Gi Cho, Eun-Chul Ahn, Sang-Young Kim, Joo-Weon Shin, Min-Ho Lee
-
Publication number: 20160148913Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: ApplicationFiled: January 29, 2016Publication date: May 26, 2016Inventors: Tae-Joo HWANG, Tae-Gyeong CHUNG, Eun-Chul AHN
-
Publication number: 20150364387Abstract: A wafer polishing method includes first polishing for polishing a wafer backside of a wafer, detecting if a defect exists on the wafer backside, determining whether a level of the detected defect is not within an allowable range, if a defect exists on the wafer backside, and second polishing for repolishing the wafer backside if the level of the defect is within an allowable range. Accordingly, a wafer may be reprocessed so that a level of defects, which may be caused by performing grinding and polishing on the wafer backside, is within an allowable range. Thus, the wafer backside may have uniform quality, and a failure rate of the wafer during a manufacturing processed may be efficiently decreased.Type: ApplicationFiled: June 2, 2015Publication date: December 17, 2015Inventors: Moon-gi CHO, Eun-chul AHN, Jung-ho CHOI
-
Publication number: 20150325518Abstract: A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width.Type: ApplicationFiled: July 14, 2015Publication date: November 12, 2015Inventors: Moon-Gi CHO, Eun-Chul AHN, Sang-Young KIM, Joo-Weon SHIN, Min-Ho LEE
-
Patent number: 9123725Abstract: A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width.Type: GrantFiled: November 25, 2013Date of Patent: September 1, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon-Gi Cho, Eun-Chul Ahn, Sang-Young Kim, Joo-Weon Shin, Min-Ho Lee
-
Publication number: 20150103494Abstract: Printed circuit boards are provided. The printed circuit board includes an insulation layer, an interconnection portion and a metal layer. The insulation layer has a flat plate shape and includes a top surface and a bottom surface. The interconnection portion is disposed on at least one of the top and bottom surfaces of the insulation layer. The interconnection portion includes a plurality of interconnection patterns. The metal layer covers the plurality of interconnection patterns of the interconnection portion. Related semiconductor packages are also provided.Type: ApplicationFiled: October 14, 2014Publication date: April 16, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee-jeong Kim, Eun-Chul AHN, Yong-Kwan LEE
-
Patent number: 8922012Abstract: In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode.Type: GrantFiled: September 30, 2010Date of Patent: December 30, 2014Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Jin-Woo Park, Eun-Chul Ahn, Dong-Kil Shin, Sun-Won Kang, Jong-Ho Lee
-
Publication number: 20140235017Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: ApplicationFiled: April 28, 2014Publication date: August 21, 2014Inventors: Tae-Joo HWANG, Tae-Gyeong CHUNG, Eun-Chul AHN
-
Publication number: 20140151845Abstract: A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width.Type: ApplicationFiled: November 25, 2013Publication date: June 5, 2014Inventors: Moon-Gi CHO, Eun-Chul AHN, Sang-Young KIM, Joo-Weon SHIN, Min-Ho LEE
-
Patent number: 8735281Abstract: A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer.Type: GrantFiled: May 2, 2013Date of Patent: May 27, 2014Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Chang-Woo Shin, Hyun-Soo Chung, Eun-Chul Ahn, Jum-Gon Kim, Jin-Ho Chun
-
Patent number: 8736035Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: GrantFiled: March 5, 2013Date of Patent: May 27, 2014Assignee: Samsung Electronics Co. Ltd.Inventors: Tae-Joo Hwang, Tae-gyeong Chung, Eun-chul Ahn
-
Publication number: 20130244419Abstract: A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer.Type: ApplicationFiled: May 2, 2013Publication date: September 19, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Woo SHIN, Hyun-Soo CHUNG, Eun-Chul AHN, Jum-Gon KIM, Jin-Ho CHUN
-
Publication number: 20130200515Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: ApplicationFiled: March 5, 2013Publication date: August 8, 2013Inventors: Tae-Joo HWANG, Tae-gyeong Chung, Eun-chul Ahn
-
Patent number: 8456012Abstract: A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer.Type: GrantFiled: September 28, 2009Date of Patent: June 4, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Chang-Woo Shin, Hyun-Soo Chung, Eun-Chul Ahn, Jum-Gon Kim, Jin-Ho Chun
-
Patent number: 8421244Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: GrantFiled: September 3, 2010Date of Patent: April 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
-
Patent number: 8367472Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.Type: GrantFiled: March 23, 2011Date of Patent: February 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Ho Lee, Dong Ho Lee, Eun Chul Ahn, Yong Chai Kwon
-
Patent number: 8354744Abstract: A stacked semiconductor package includes an upper unit package and a lower unit package. The lower unit package includes a substrate, a semiconductor chip disposed on an upper surface of the substrate, terminal pads arranged on an upper surface of the semiconductor chip, protrusions formed on the terminal pads, a protective layer formed on the substrate and covering the semiconductor chip and the protrusions, and openings formed in the protective layer and exposing the protrusions. The upper unit package includes a substrate, ball lands provided on a lower surface of the substrate, and solder balls formed on the ball lands. The solder balls of the upper unit package are inserted into the openings of the lower unit package to be connected to the protrusions of the lower unit package.Type: GrantFiled: February 23, 2010Date of Patent: January 15, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Byung-Woo Lee, Young-Lyong Kim, Eun-Chul Ahn
-
Patent number: 8344497Abstract: A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.Type: GrantFiled: September 29, 2008Date of Patent: January 1, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Pyoung-Wan Kim, Eun-Chul Ahn, Teak-Hoon Lee, Chul-Yong Jang