Abstract: A power semiconductor package is disclosed. The power semiconductor package includes a leadframe having partially etched segments and at least one non-etched segment, a first semiconductor die having a first power transistor and a driver integrated circuit (IC) monolithically formed thereon, a second semiconductor die having a second power transistor, wherein the first semiconductor die and the second semiconductor die are configured for attachment to the partially etched segments, and wherein the partially etched segments and the at least one non-etched segment enable the first semiconductor die to be coupled to the second semiconductor die by a legless conductive clip.

Abstract: There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.

Abstract: In one implementation, a semiconductor package includes an integrated circuit (IC) attached to a die paddle segment of a first patterned conduct carrier and coupled to a switch node segment of the first patterned conductive carrier by an electrical connector. In addition, the semiconductor package includes a second patterned conductive carrier situated over the IC, a magnetic material situated over the second patterned conductive carrier, and a third patterned conductive carrier situated over the magnetic material. The second patterned conductive carrier and the third patterned conductive carrier are electrically coupled so as to form windings of an integrated inductor in the semiconductor package.

Abstract: In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier.

Abstract: One disclosed implementation is a power semiconductor package including a sync transistor having a drain on its top surface and a source and a gate on its bottom surface. The source of the sync transistor is configured for attachment to a first partially etched leadframe segment and the gate of the sync transistor is configured for attachment to a second partially etched leadframe segment. A control transistor has a source and a gate on its top surface and a drain on its bottom surface. The drain of the control transistor is configured for attachment to a third partially etched leadframe segment. A first conductive clip extends to the substrate and is situated over the drain of the sync transistor and the source of the control transistor, the first conductive clip coupling the drain of the sync transistor and the source of the control transistor to the substrate without using a leadframe.

Abstract: Disclosed is a power semiconductor package including a power transistor having a first power electrode and a gate electrode on its top surface and a second power electrode on its bottom surface. The second power electrode is configured for attachment to a partially etched leadframe segment, where the partially etched leadframe segment is attached to a substrate. A conductive clip is situated over the first power electrode and extends to the substrate in order to couple the first power electrode to the substrate without using a leadframe.

Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

Abstract: A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

Abstract: One disclosed implementation is a power semiconductor package including a sync transistor having a drain on its top surface and a source and a gate on its bottom surface. The source of the sync transistor is configured for attachment to a first partially etched leadframe segment and the gate of the sync transistor is configured for attachment to a second partially etched leadframe segment. A control transistor has a source and a gate on its top surface and a drain on its bottom surface. The drain of the control transistor is configured for attachment to a third partially etched leadframe segment. A first conductive clip extends to the substrate and is situated over the drain of the sync transistor and the source of the control transistor, the first conductive clip coupling the drain of the sync transistor and the source of the control transistor to the substrate without using a leadframe.

Abstract: A semiconductor package includes an output inductor placed over a support substrate, a power semiconductor die having a bottom surface situated on the support substrate and a top surface having an active region, where the output inductor is coupled to the active region on the top surface of the support substrate, and where the support substrate includes a plurality of bar vias. The output inductor is a packaged component having at least two leads in electrical connection with the active region of the power semiconductor die. The support substrate further includes routing conductors in electrical connection with the active region of the power semiconductor die. The power semiconductor die includes a control transistor and a sync transistor connected in a half-bridge.

Abstract: In one implementation, a semiconductor package includes a first conductive carrier including a first die paddle of the semiconductor package, and a control transistor having a drain attached to the first die paddle. The semiconductor package also includes a second conductive carrier attached to the first conductive carrier and including a second die paddle of the semiconductor package, and a sync transistor having a drain attached to the second die paddle. The second die paddle couples a source of the control transistor to the drain of the sync transistor.

Abstract: In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section conductive carrier. The first and second sections of the multi-section conductive carrier sink heat generated by the control and sync transistors. The first and second sections of the multi-section conductive carrier are electrically connected only through a mounting surface attached to the power semiconductor package. Another implementation of the power semiconductor package includes a driver IC coupled to a third section of the multi-section conductive carrier. A method for fabricating the power semiconductor package is also disclosed.

Abstract: In one implementation, a method of fabricating a power semiconductor package is disclosed. The method includes providing a conductive carrier array including a plurality of power modules held together with connecting bars, where each of the plurality of power modules includes a control transistor, a sync transistor, and a driver IC. The method further includes overlying on the conductive carrier array a heat spreader array including a plurality of power electrode heat spreaders such that each of the plurality of power electrode heat spreaders couples a drain of the sync transistor to a source of the control transistor in each power module.

Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.

Abstract: An integrated dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a driver integrated circuit (IC) paddle configured to support a driver IC for controlling each of the control FETs and each of the sync FETs. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

Abstract: In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier.

Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.

Abstract: In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain.

Abstract: In one implementation, a power semiconductor package includes a power transistor having a first power electrode and a gate electrode on its bottom surface, and a second power electrode on its top surface. The first power electrode is configured for attachment to a first partially etched conductive carrier segment and the gate electrode is configured for attachment to a second partially etched conductive carrier segment. The power semiconductor package also includes a power electrode heat spreader situated over the second power electrode and configured for attachment to a power electrode conductive carrier segment.

Abstract: In one implementation, a semiconductor package includes a first conductive carrier including a first die paddle of the semiconductor package, and a control transistor having a drain attached to the first die paddle. The semiconductor package also includes a second conductive carrier attached to the first conductive carrier and including a second die paddle of the semiconductor package, and a sync transistor having a drain attached to the second die paddle. The second die paddle couples a source of the control transistor to the drain of the sync transistor.