Patents by Inventor Fabrice Letertre

Fabrice Letertre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120329243
    Abstract: The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate.
    Type: Application
    Filed: June 18, 2012
    Publication date: December 27, 2012
    Applicant: SOITEC
    Inventors: Fabrice Letertre, Didier Landru
  • Publication number: 20120241821
    Abstract: A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10?3 ohm·cm and a thermal conductivity of greater than 100 W·m?1·K?1, a bonding layer, a first seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, a second seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and an active layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and being present in a thickness of between 3 and 100 micrometers. The materials of the support substrate, the bonding layer and the first seed layer are refractory at a temperature of greater than 750° C., the active layer and second seed layer have a difference in lattice parameter of less than 0.005 ?, the active layer is crack-free, and the heterostructure has a specific contact resistance between the bonding layer and the first seed layer that is less than or equal to 0.1 ohm·cm2.
    Type: Application
    Filed: December 1, 2010
    Publication date: September 27, 2012
    Applicant: SOITEC
    Inventors: Jean-Marc Bethoux, Fabrice Letertre, Chris Werkhoven, Ionut Radu, Oleg Kononchuck
  • Patent number: 8252664
    Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing an support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the substrate.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: August 28, 2012
    Assignee: Soitec
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
  • Publication number: 20120214291
    Abstract: A method for relaxing a layer of a strained material. The method includes depositing a first low-viscosity layer on a first face of a strained material layer; bonding a first substrate to the first low-viscosity layer to form a first composite structure; subjecting the composite structure to heat treatment sufficient to cause reflow of the first low-viscosity layer so as to at least partly relax the strained material layer; and applying a mechanical pressure to a second face of the strained material layer wherein the second face is opposite to the first face and with the mechanical pressure applied perpendicularly to the strained material layer during at least part of the heat treatment to relax the strained material.
    Type: Application
    Filed: April 27, 2012
    Publication date: August 23, 2012
    Applicant: SOITEC
    Inventors: Fabrice Letertre, Carlos Mazure, Michael R. Krames, Melvin B. McLaurin, Nathan F. Gardner
  • Patent number: 8216368
    Abstract: A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: July 10, 2012
    Assignee: Soitec
    Inventors: Bruce Faure, Fabrice Letertre
  • Publication number: 20120112205
    Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.
    Type: Application
    Filed: January 4, 2012
    Publication date: May 10, 2012
    Applicant: SOITEC
    Inventor: Fabrice Letertre
  • Publication number: 20120100692
    Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.
    Type: Application
    Filed: January 4, 2012
    Publication date: April 26, 2012
    Applicant: SOITEC
    Inventor: Fabrice Letertre
  • Patent number: 8154022
    Abstract: A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: April 10, 2012
    Assignee: Soitec
    Inventors: Chantal Arena, Fabrice Letertre
  • Publication number: 20120058621
    Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing an support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the substrate.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 8, 2012
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
  • Publication number: 20120048906
    Abstract: An automatic cutting device is described for cutting an assembly. The assembly includes a material having a weakened zone therein that defines a useful layer and being attached to a source substrate. The cutting device includes a cutting mechanism and a holding and positioning mechanism operatively associated with the cutting mechanism. The holding and positioning mechanism positions the material so that the cutting mechanism detaches the layer from the source substrate along the weakened zone. The cutting device also includes a control mechanism for adjusting at least two different portions of the assembly during detachment of the layer to facilitate a more precise detachment.
    Type: Application
    Filed: November 10, 2011
    Publication date: March 1, 2012
    Inventors: Olivier Rayssac, Fabrice Letertre
  • Patent number: 8114754
    Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: February 14, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Fabrice Letertre
  • Publication number: 20120012048
    Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing an support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the substrate.
    Type: Application
    Filed: September 27, 2011
    Publication date: January 19, 2012
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
  • Patent number: 8093687
    Abstract: Methods for transferring of a useful layer from a support are described. In an embodiment, the method includes for facilitating transfer of a useful layer from a support by providing an interface in a first support to define a useful layer; and forming a peripheral recess on the first support below the interface so that the periphery of the interface is exposed to facilitate removal and transfer of the useful layer. An epitaxial layer can be formed on the useful layer after forming the recess, with the width and depth of the recess being sufficient to accommodate the volume of residual material resulting from formation of the epitaxial layer without covering the periphery of the interface. Alternatively, an epitaxial layer can be formed on the useful layer after forming the recess, wherein the peripheral recess is configured for receiving sufficient residual material from the epitaxial layer to prevent bonding between the residual material and the useful layer.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Olivier Rayssac
  • Patent number: 8083115
    Abstract: An automatic cutting device is described for cutting an assembly. The assembly includes a material having a weakened zone therein that defines a useful layer and being attached to a source substrate. The cutting device includes a cutting mechanism and a holding and positioning mechanism operatively associated with the cutting mechanism. The holding and positioning mechanism positions the material so that the cutting mechanism detaches the layer from the source substrate along the weakened zone. The cutting device also includes a control mechanism for adjusting at least two different portions of the assembly during detachment of the layer to facilitate a more precise detachment.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: December 27, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Olivier Rayssac, Fabrice Letertre
  • Publication number: 20110291247
    Abstract: The present invention relates to a method for the formation of an at least partially relaxed strained material layer, the method comprising the steps of providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.
    Type: Application
    Filed: January 11, 2010
    Publication date: December 1, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Fabrice Letertre, Bruce Faure, Pascal Guenard
  • Patent number: 8048693
    Abstract: The present invention provides methods for relaxing a strained-material layer and structures produced by the methods. Briefly, the methods include depositing a first low-viscosity layer that includes a first compliant material on the strained-material layer, depositing a second low-viscosity layer that includes a second compliant material on the strained-material layer to form a first sandwiched structure and subjecting the first sandwiched structure to a heat treatment such that the reflow of the first and the second low-viscosity layers permits the strained-material layer to at least partly relax.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: November 1, 2011
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Carlos Mazure
  • Publication number: 20110237008
    Abstract: A method of fabricating a device by providing an auxiliary substrate having a metal nitride layer disposed thereon where the nitride layer has a nitrogen face and an opposite face and a dislocation density that is less than about 106, with the nitrogen face of the nitride layer facing the auxiliary substrate; depositing at least one epitaxial nitride layer on the exposed opposite face of the nitride layer of the structure; depositing a further metal layer over at least a portion of the epitaxial nitride layer(s); bonding a final substrate on the deposited metal layer; and removing the auxiliary substrate to form the device from the final substrate and deposited layers. Preferably, the device that is formed includes a LED or laser.
    Type: Application
    Filed: June 7, 2011
    Publication date: September 29, 2011
    Inventors: Fabrice Letertre, Bruce Faure
  • Publication number: 20110180911
    Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.
    Type: Application
    Filed: April 7, 2011
    Publication date: July 28, 2011
    Inventors: Pascal Guenard, Bruce Faure, Fabrice Letertre, Michael R. Krames, Nathan F. Gardner, Melvin B. McLaurin
  • Patent number: 7981767
    Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: July 19, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Pascal Guenard, Bruce Faure, Fabrice Letertre, Michael R. Krames, Nathan F. Gardner, Melvin B. McLaurin
  • Publication number: 20110171812
    Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal expansion of the support substrate and of the working layer. In another embodiment, the method includes providing a source substrate with a weakened zone defining a nucleation layer, bonding a support substrate to the source substrate, detaching the nucleation layer and support substrate at the weakened zone by applying laser irradiation stress, depositing a semiconductor material upon the nucleation layer, bonding a target substrate to the deposited layer and removing the support substrate and nucleation layer. The result is a semiconductor substrate that includes the layer of semiconductor material on a support or target substrate.
    Type: Application
    Filed: January 5, 2011
    Publication date: July 14, 2011
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac